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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37754M8C-XXXGP is a single-chip microcomputer designed with high-performance CMOS silicon gate technology. This is housed in a 100-pin plastic molded QFP. This microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing, and the bus interface unit enhances the memory access efficiency to execute instructions fast. In addition to the 7700 Family basic instructions, the M37754M8CXXXGP has 6 special instructions which contain instructions for signed multiplication/division; these added instructions improve the servo arithmetic performance to control hard disk drives and so on. This microcomputer also include the ROM, RAM, multiple-function timers, motor control function, serial I/O, A-D converter, D-A converter, and so on. The differences between M37754M8C-XXXGP, M37754M8C-XXXHP, M37754S4CGP and M37754S4CHP are listed in the table on the next page: the internal ROM, usable processor mode, and package. Therefore, the following descriptions will be for the M37754M8CXXXGP unless otherwise noted.
* Instruction execution time
The fastest instruction at 40 MHz frequency ...................... 100 ns
* Single power supply ...................................................... 5V 10 % * Low power dissipation (at 40 MHz frequency) ....... 125 mW (Typ.) * Interrupts ........................................................... 21 types, 7 levels * Multiple-function 16-bit timer ................................................... 5+3 * * * * * *
(three-phase motor drive waveform or pulse motor control waveform output) Serial I/O (UART or clock synchronous) ..................................... 2 10-bit A-D converter ............................................ 8-channel inputs 8-bit D-A converter ............................................ 2-channel outputs 12-bit watchdog timer Programmable input/output (ports P0--P11) ......................................................................... 87 Small package [M37754M8C-XXXHP] ................................. 100-pin fine pitch QFP (read pitch : 0.5 mm)
APPLICATION
Control devices for personal computer peripheral equipment such as CD-ROM drives, hard disk drives, high density FDD, printers Control devices for office equipment such as copiers and facsimiles Control devices for industrial equipment such as communication and measuring instruments Control devices for equipment required for motor control such as inverter air conditioner and general purpose inverter
DISTINCTIVE FEATURES
* Number of basic machine instructions .................................... 109 * Memory size
(103 basic instructions of 7700 Family + 6 special instructions) ROM ................................................ 60 Kbytes RAM ................................................ 2048 bytes
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8 P11/A9 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/A16 P21/A17 P22/A18 P23/A19 P27/A23 P100/D0/LA0 P101/D1/LA1 P102/D2/LA2 P103/D3/LA3 P104/D4/LA4 P105/D5/LA5 P106/D6/LA6 P107/D7/LA7 P110/D8
M37754M8C-XXXGP PIN CONFIGURATION (TOP VIEW)
P87/TXD1 P86/RXD1 P85/CLK1 P84/CTS1/RTS1/DA1/INT4 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1/DA0 VCC AVCC VREF AVSS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
M37754M8C-XXXGP or M37754S4CGP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P111/D9 P112D10 P113/D11 P114/D12 P115/D13 P116/D14 P117/D15 P30/WR P31/BHE P32/ALE P33/HLDA VCC VSS E/RD XOUT XIN RESET CNVSS BYTE P40/HOLD
P70/AN0 P95/INT3/KI4 P94/CS4/RTP13 P93/CS3/A22/RTP12 P92/CS2/A21/U/RTP11 P91/CS1/A20/V/RTP10 P90/CS0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN/W/RTP03 P52/TA1OUT/U/RTP02 P51/TA0IN/V/RTP01 P50/TA0OUT/W/RTP00 P47 P46 P45 P44 P43 P42/1 P41/RDY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Outline 100P6S-A
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37754M8C-XXXHP PIN CONFIGURATION (TOP VIEW)
75 P03/A3 74 P04/A4 73 P05/A5 72 P06/A6 71 P07/A7 70 P10/A8 69 P11/A9 68 P12/A10 67 P13/A11 66 P14/A12 65 P15/A13 64 P16/A14 63 P17/A15 62 P20/A16 61 P21/A17 60 P22/A18 59 P23/A19 58 P27/A23 57 P100/D0/LA0 56 P101/D1/LA1 55 P102/D2/LA2 54 P103/D3/LA3 53 P104/D4/LA4 52 P105/D5/LA5 51 P106/D6/LA6 P02/A2 76 P01/A1 77 P00/A0 78 P87/TXD1 79 P86/RXD1 80 P85/CLK1 81 P84/CTS1/RTS1/DA1/INT4 82 P83/TXD0 83 P82/RXD0/CLKS0 84 P81/CLK0 85 P80/CTS0/RTS0/CLKS1/DA0 86 87 VCC 88 AVCC VREF 89 90 AVSS 91 VSS P77/AN7/ADTRG 92 P76/AN6 93 P75/AN5 94 P74/AN4 95 P73/AN3 96 P72/AN2 97 P71/AN1 98 P70/AN0 99 P95/INT3/KI4 100
M37754M8C-XXXHP or M37754S4CHP
50 P107/D7/LA7 49 P110/D8 48 P111/D9 47 P112/D10 46 P113/D11 45 P114/D12 44 P115/D13 43 P116/D14 42 P117/D15 41 P30/WR 40 P31/BHE 39 P32/ALE 38 P33/HLDA 37 VCC 36 VSS 35 E/RD 34 XOUT 33 XIN 32 RESET 31 CNVSS 30 BYTE 29 P40/HOLD 28 P41/RDY 27 P42/1 26 P43
Differences between M37754M8C-XXXGP, M37754M8C-XXXHP, M37754S4CGP, and M37754S4CHP
Product M37754M8C-XXXGP M37754M8C-XXXHP M37754S4CGP M37754S4CHP Internal ROM Equipped (60 Kbytes) Not equipped (External ROM) * * * * Usable processor mode Single-chip mode Memory expansion mode Microprocessor mode Microprocessor mode Package 100-pin QFP (100P6S-A) 100-pin fine pitch QFP (100P6Q-A) 100-pin QFP (100P6S-A) 100-pin fine pitch QFP (100P6Q-A)
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P94/CS4/RTP13 1 P93/CS3/A22/RTP12 2 P92/CS2/A21/U/RTP11 3 P91/CS1/A20/V/RTP10 4 P90/CS0 5 P67/TB2IN 6 P66/TB1IN 7 P65/TB0IN 8 P64/INT2 9 P63/INT1 10 P62/INT0 11 P61/TA4IN 12 P60/TA4OUT 13 P57/TA3IN/KI3 14 P56/TA3OUT/KI2 15 P55/TA2IN/KI1 16 P54/TA2OUT/KI0 17 P53/TA1IN/W/RTP03 18 P52/TA1OUT/U/RTP02 19 P51/TA0IN/V/RTP01 20 P50/TA0OUT/W/RTP00 21 P47 22 P46 23 P45 24 P44 25
Outline 100P6Q-A
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus width select input BYTE
Data Bus(Even) Data Bus(Odd)
Input/Output port P0 Input/Output port P9 Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P11 Input/Output Input/Output Input/Output Input/Output port P3 port P2 port P1 port P10 P0 (8) P9(6) P8(8) P7(8) P6(8) P5(8) P4(8) P11(8) P10 (8) P3 (4) P2 (5) P1 (8)
Data Buffer DBH(8) Data Buffer DBL(8)
Reference voltage input VREF
Instruction Register(8)
Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8)
(5V) AVCC
Address Bus (0V) AVSS Incrementer(24)
D-A1 Converter(8)
UART 1(9)
Data Address Register DA(24) CNVSS
(0V) VSS
Incrementer/Decrementer(24) Program Counter PC(16) Program Bank Register PG(8) Data Bank Register DT(8)
WatchdogTimer Timer TB2(16) Timer TB1(16)
Timer TA1(16)
ROM 60 Kbytes
RAM 2048 Bytes
(5V) VCC
Input Buffer Register IB(16)
Reset input RESET
Timer TA4(16)
Timer TA3(16)
Timer TA2(16)
Processor Status Register PS(11) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16)
BLOCK DIAGRAM Enable output Clock output
E
Index Register X(16) Clock Generating Circuit Accumulator B(16) Accumulator A(16)
XOUT
Clock input XIN
Arithmetic Logic Unit(16)
Timer TA0(16)
Timer TB0(16)
UART 0(9)
A-D Converter(10)
D-A0 Converter(8)
Program Address Register PA(24)
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37754M8C-XXXGP
Parameter Number of basic machine instructions Instruction execution time ROM (Note 1) Memory size RAM P0, P1, P4 - P8, P10, P11 P2 Input/Output ports (Note 2) P3 P9 TA0, TA1, TA2, TA3, TA4 Multiple-function timers TB0, TB1, TB2 Serial I/O A-D converter D-A converter Watchdog timer Short-circuit prevention time set timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Input/Output withstand voltage Output current Functions 109 100 ns (the fastest instruction at external clock 40 MHz frequency) 60 Kbytes 2048 bytes 8-bit x 9 5-bit x 1 4-bit x 1 6-bit x 1 16-bit x 5 16-bit x 3 (UART or clock synchronous serial I/O) x 2 10-bit x 1(8 channels) 8-bit x 2 12-bit x 1 8-bit x 3 5 external types, 16 internal types (Each interrupt can be set to priority levels 0 - 7.) Built-in (externally connected to a ceramic resonator or quartz crystal resonator) 5 V10 % 125 mW(at external clock 40 MHz frequency) 5V 5 mA Maximum 16 Mbytes -20 to 85 C CMOS high-performance silicon gate process 100-pin plastic molded QFP
Notes 1: The M37754S4CGP and the M37754S4CHP are not equipped with ROM. 2: Input/Output ports for the M37754S4CGP and the M37754S4CHP are as shown below : * P5-P8, P11 (8-bit x 5) * P4 (5-bit x 1) * P9 (6-bit x 1)
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (MICROCOMPUTER MODE)
Pin VCC, VSS CNVSS RESET XIN XOUT E Name Power supply CNVSS input Reset input Clock input Clock output Enable output Input/ Output Input Input Input Output Output Functions Supply 5 V10 % to VCC and 0 V to VSS. This pin controls the processor mode. Connect to VSS for single-chip mode or memory expansion mode. Connect to VCC for microprocessor mode and external ROM version. This is reset input pin. The microcomputer is reset when supplying "L" level to this pin. These are I/O pins of internal clock generating circuit. Connect a ceramic or quartzcrystal resonator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. _ This pin outputs enable signal E, which indicates access state of data bus for single-chip mode. ___ This pin outputs RD signal for memory expansion mode or microprocessor mode. This pin determines whether the external data bus is 8-bit width or 16-bit width for memory expansion mode or microprocessor mode. The width is 16 bits when "L" signal inputs and 8 bits when "H" signal inputs. Power supply for the A-D converter and the D-A converter. Connect AVCC to VCC and AVSS to VSS externally. This is reference voltage input pin for the A-D converter and the D-A converter. In single-chip mode, port P0 is an 8-bit I/O port. This port has an I/O direction register and each pin can be programmed for input or output. These ports are in the input mode when reset. Address (A0 - A7) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A8 A15) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. Address (A16 A19, A23) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port _____ memory P0. In ___ ____ expansion mode or microprocessor mode, WR, BHE , ALE, and HLDA signals are output. In single-chip mode, these pins have the same functions as port P0. In _____ memory expansion mode or micro processor mode, P40, P41, and P42 become HOLD and ____ RDY input pins, and clock 1 output pin respectively. Functions of other pins are the same as in single-chip mode. In memory expansion mode, P42 can be programmed as I/O port. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for timer A0, timer A1, timer A2, timer A3, output pins for motor drive waveform, and input pins for key input interrupt. In addition to having the same functions as port P0 in single-chip mode, these pins ____ also ____function as I/O pins for timer A4, input pins for external interrupt input INT0, ____ INT1, and INT2, and input pins for timer B0, timer B1, and timer B2. In addition to having the same functions as port P0 in single-chip mode, these pins also function as input pins for A-D converter. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for UART0, UART1, output pins for D-A converter, and ____ input pin for INT4. In addition to having the same functions as port P0 in single-chip mode, these pins ____ also function as input pin for INT3, output pins for motor drive waveform. In memory expansion mode and microprocessor mode, these pins can be ___ ___ programmed as address (A20 - A22) or output pins for CS0 - CS4
BYTE (Note) AVCC, AVSS VREF P00 - P07
Bus width select input
Input
Analog supply input Reference voltage input I/O port P0 Input I/O
P10 - P17 P20 - P23, P27 P30 - P33
I/O port P1 I/O port P2 I/O port P3
I/O I/O I/O
P40 - P47
I/O port P4
I/O
P50 - P57
I/O port P5
I/O
P60 - P67
I/O port P6
I/O
P70 - P77 P80 - P87
I/O port P7 I/O port P8
I/O I/O
P90 - P95
I/O port P9
I/O
Note: It is impossible to change the input level of the BYTE pin in each bus cycle. In other words, bus width cannot be switched dynamically. Fix the input level of the BYTE pin to "H" or "L" according to the bus width used.
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin
Name
P100 - P107 I/O port P10
Input/ Output I/O
Functions In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins become data I/O pins and operate as follows: (1) When using 16-bit width as external data bus width: Accessing external memory Pins' value is input into low-order internal data bus (DB0 to DB7). Value of low-order internal data bus (DB0 to DB7) is output to these pins. Accessing internal memory These pins become high impedance. Value of internal data bus is output to these pins.
* *
(2) When using 8-bit width as external data bus width: Accessing external memory Pins' value is input into internal data bus. The value is input into low-order internal data bus (DB0 to DB7) when accessing an even address; it is input into high-order internal data bus (DB8 to DB15) when accessing an odd address. Value of internal data bus is output to these pins. The value of low-order internal data bus (DB0 to DB7) is output when accessing an even address; the value of high-order internal data bus (DB8 to DB15) is output when accessing an odd address. Accessing internal memory These pins become high impedance. Value of internal data bus is output to these pins. When the external bus width is 8 bits, the mode where low-order address ___ ___ (LA0 - LA7) is output when RD or WR output is "H" and data (D0 - D7) is ___ ___ input/output when RD or WR output is "L" can be selected in specified external memory area access cycle.
*
*
P110 - P117 I/O port P11
I/O
In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins operate as follows: (1) When using 16-bit width as external data bus width Accessing external memory The value is input into high-order internal data bus (DB8 to DB15) when accessing an odd address; these pins enter high impedance state when not accessing an odd address. Value of high-order internal data bus (DB8-DB15) is output to these pins. Accessing internal memory These pins enter high impedance state. Value of internal data bus is output to these pins. (2) When using 8-bit width as external data bus width These pins become I/O port P110 - P117.
*
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37754M8C-XXXGP contains the following devices on a single chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D converter, D-A converter, I/O ports, clock generating circuit and others. Each of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space is 16 Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered from 016 to FF16. Internal ROM, internal RAM, and control registers for internal peripheral devices are assigned to bank 016. The 60-Kbyte area from addresses 100016 to FFFF16 is the internal ROM.
Addresses FFD216 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Refer to the section on interrupts for details. The 2048-byte area from addresses 8016 to 87F16 contains the internal RAM. In addition to storing data, the RAM is used as stack during a subroutine call, or interrupts. Assigned to addresses 016 to 7F16 are peripheral devices such as I/O ports, A-D converter, D-A converter, UART, timer, and interrupt control registers. Additionally the internal ROM area can be modified by software. Refer to the section on ROM area modification function for details. A 256-byte direct page area can be allocated anywhere in bank 016 using the direct page register DPR. In direct page addressing mode, the memory in the direct page area can be accessed with two words thus reducing program steps.
Bank 016
Bank 116
FE000016 Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16
* * * * * * * * * * * * *

00000016
00000016 00007F16 00008016 Internal RAM 2048 bytes
00000016 Peripherai devices control registers see Fig. 2 for further information 00007F16
00FFFF16 01000016
00087F16 Interrupt vector table 00FFD216 00100016 INT4 INT3
A-D
01FFFF16
UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Internal ROM 60 Kbytes Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 Watchdog timer DBC BRK instruction Zero divide 00FFFF16 00FFFE16 RESET
Note: Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
Fig. 1 Memory map
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation) 000000 000001 Port P0 register 000002 Port P1 register 000003 000004 Port P0 direction register 000005 Port P1 direction register 000006 Port P2 register 000007 Port P3 register 000008 Port P2 direction register 000009 Port P3 direction register Port P4 register 00000A Port P5 register 00000B Port P4 direction register 00000C Port P5 direction register 00000D Port P6 register 00000E Port P7 register 00000F Port P6 direction register 000010 Port P7 direction register 000011 Port P8 register 000012 Port P9 register 000013 Port P8 direction register 000014 Port P9 direction register 000015 Port P10 register 000016 Port P11 register 000017 000018 Port P10 direction register Port P11 direction register 000019 00001A Waveform output mode register 00001B Dead-time timer 00001C Pulse output data register 1 Pulse output data register 0 00001D A-D control register 0 00001E A-D control register 1 00001F 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F UART0 transmit/receive mode register 000030 UART0 baud rate register 000031 000032 UART0 transmit buffer register 000033 UART0 transmit/receive control register 0 000034 UART0 transmit/receive control register 1 000035 000036 UART0 receive buffer register 000037 UART1 transmit/receive mode register 000038 UART1 baud rate register 000039 00003A UART1 transmit buffer register 00003B UART1 transmit/receive control register 0 00003C UART1 transmit/receive control register 1 00003D 00003E UART1 receive buffer register 00003F
Address (Hexadecimal notation) Count start register 000040 000041 One-shot start register 000042 000043 Up-down register 000044 000045 Timer A write register 000046 Timer A0 register 000047 000048 Timer A1 register 000049 00004A Timer A2 register 00004B 00004C Timer A3 register 00004D 00004E Timer A4 register 00004F 000050 Timer B0 register 000051 000052 Timer B1 register 000053 000054 Timer B2 register 000055 Timer A0 mode register 000056 Timer A1 mode register 000057 Timer A2 mode register 000058 Timer A3 mode register 000059 Timer A4 mode register 00005A Timer B0 mode register 00005B Timer B1 mode register 00005C Timer B2 mode register 00005D Processor mode register 0 00005E Processor mode register 1 00005F Watchdog timer register 000060 Watchdog timer frequency select register 000061 Chip select control register 000062 Chip select area register 000063 Comparator function select register 000064 Reserved area (Note) 000065 Comparator result register 000066 Reserved area (Note) 000067 D-A register 0 000068 000069 D-A register 1 00006A 00006B Particular function select register 0 00006C Particular function select register 1 00006D INT4 interrupt control register 00006E INT3 interrupt control register 00006F A-D interrupt control register 000070 UART0 trasmit interrupt control register 000071 UART0 receive interrupt control register 000072 UART1 trasmit interrupt control register 000073 UART1 receive interrupt control register 000074 Timer A0 interrupt control register 000075 Timer A1 interrupt control register 000076 Timer A2 interrupt control register 000077 Timer A3 interrupt control register 000078 Timer A4 interrupt control register 000079 Timer B0 interrupt control register 00007A Timer B1 interrupt control register 00007B Timer B2 interrupt control register 00007C INT0 interrupt control register 00007D INT1 interrupt control register 00007E INT2 interrupt control register 00007F Note: Do not write to this address.
Fig. 2 Location of peripheral devices and interrupt control registers
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of these registers is described below.
In index addressing mode, register X is used as the index register and the contents of this address is added to obtain the real address. Index register X functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate).
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. The data length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is "0" and as an 8-bit register when flag m is "1". Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., is executed mainly through the accumulator.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later. In index addressing mode, register Y is used as the index register and the contents of this address is added to obtain the real address. Index register Y functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate).
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later.
15 AH 15 BH 15 XH 15 YH 15 7 PG 7 DT 0 Data bank register DT 0 Program bank register PG 15
7 AL 7 BL 7 XL 7 YL
0 Accumulator A 0 Accumulator B 0 Index register X 0 Index register Y 0 Stack pointer S 0 Program counter PC 0 Direct page register DPR 0 Z C Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL
S PC 15 15 00000 DPR 7 IPL2 IPL1 IPL0 N V m x D
I
Fig. 3 Register structure
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of a flag to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V, and N. The details of each bit of the processor status register are described below.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through bus interface unit. This is described later.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is increased by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to "1", all interrupts except ___ watchdog timer, DBC, and software interrupt are disabled. This flag is set to "1" automatically when there is an interrupt. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing modes, the data bank register (DT) is used to specify a part of the memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is "0". If it is "1", decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. Arithmetic operation is performed using four digits when the data length flag m is "0" and with two digits when it is "1". Decimal adjust is automatically performed. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used as the base address of a 256-byte direct page area. The direct page area is allocated in bank 016, but when the contents of DPR is FF0116 or greater, the direct page area spans across bank 016 and bank 116. All direct addressing modes use the contents of the direct page register (DPR) to generate the data address. If the low-order 8 bits of the direct page register (DPR) is "0016", the number of cycles required to generate an address is minimized. Normally the low-order 8 bits of the direct page register (DPR) is set to "0016".
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5. Index register length flag (x)
The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is "0" and as 8bit registers when it is "1". This flag can be set and reset with the SEP and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than the processor interrupt priority. When interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details. Note: Fix bits 11 to 15 of the processor status register (PS) to "0".
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16-bit when flag m is "0" and 8-bit when it is "1". This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
BUS INTERFACE UNIT 7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. If data length flag m is "0", the overflow flag is set when the result of addition or subtraction is outside the range between -32768 and +32767. If data length flag m is "1", the overflow flag is set when the result of addition or subtraction is outside the range between -128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP instructions. Additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of -2147483648 to +2147483647 in the RMPA operation. The CPU operates on the basis of internal clock CPU frequency. In order to speed-up processing, a bus interface unit is used to prefetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre-fetches instructions. Figure 4 shows the relationship between the CPU and the bus interface unit. The bus interface unit controls buses to access memories easily. Refer to BUS CYCLE on the following pages. The bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from memory and stores it in the instruction queue buffer, obtains data from memory and stores it in the data buffer, or writes the data form the data buffer to the memory.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag m is "0", data's bit 15 is "1". If data length flag m is "1", data's bit 7 is "1".) It is reset in all other cases. It can also be set and reset with the SEP and CLP instructions.
D'8-D'15 D'0-D'7 A'0-A'23
D8-D15 D0-D7 A0-A23
BHE CPU Bus interface unit WR RD Control signal ALE BYTE HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
__
Figure 5 shows basic waveforms of the bus interface unit. The RD signal becomes "L" when the bus interface unit reads an instruction ___ code or data from memory. The WR signal becomes "L" when the bus interface unit writes data to memory. Waveforms (1) and (3) in Figure 5 are used to access a single byte or two bytes simultaneously. To read or write two bytes simultaneously, the first address accessed must be even. Furthermore, when accessing an external memory area in memory expansion mode or microprocessor mode, set the bus width select input pin
(BYTE) to "L" (external data bus width = 16 bits). The internal memory area is always treated as 16-bit bus width regardless of BYTE. When performing 16-bit data read or write, if the conditions for simultaneously accessing two bytes are not satisfied, waveforms (2) and (4) are used to access each byte, one by one. However, when prefetching the instruction code, if the address of the instruction code is odd, only one byte is read in the instruction queue buffer.
(1)
WR
(2)
WR
RD Internal address bus (A0 - A23) Internal data bus (D0 - D7) Internal data bus (D8 - D15)
RD Internal address bus (A0 - A23) Internal data bus (D0 - D7) Internal data bus (D8 - D15)
Address
Address (odd)
Address (even)
Data (even)
Invalid data
Data (even)
Data (odd)
Data (odd)
Invalid data
(3)
WR
(4)
WR
RD Internal address bus (A0 - A23) Internal data bus (D0 - D7) Internal data bus (D8 - D15)
RD Internal address bus (A0 - A23) Internal data bus (D0 - D7) Internal data bus (D8 - D15)
Address
Address (odd)
Address (even)
Data (even)
Invalid data
Data (even)
Data (odd)
Data (odd)
Invalid data
Fig. 5 Basic waveforms of bus interface unit
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction code read, data read, and data write are described below. Instruction code read will be described first. The CPU obtains instruction codes from the instruction queue buffer and executes them. The CPU notifies the bus interface unit that CPU is requesting an instruction code during an instruction code request cycle. If the requested instruction code is not yet stored in the instruction queue buffer, the bus interface unit halts the CPU until it can store more instructions than requested in the instruction queue buffer. Even if there is no instruction code request from the CPU, the bus interface unit reads instruction codes from memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. This is referred to as instruction pre-fetching. Normally, when reading an instruction code from memory, if the accessed address is even, the next odd address is read together with the instruction code and stored in the instruction queue buffer. However, in memory expansion mode or microprocessor mode, if the bus width select input (BYTE) is "H" and external data bus width is 8 bits, and if the address to be read is in external memory area or is odd, only one byte is read and stored in the instruction queue buffer. Data read and write are described below. The CPU notifies the bus interface unit when performing data read or write. At this time, the bus interface unit halts the CPU if the bus interface unit is already using the bus or if there is a request with higher priority. When data read or write is enabled, the bus interface unit performs data read or write. During data read, the CPU waits until the entire data is stored in the data buffer. The bus interface unit sends the address sent from the ___ CPU to the address bus. Then it reads the memory when the RD signal is "L" and stores the result in the data buffer. During data write, the CPU writes the data in the data buffer and the bus interface unit writes it to memory. Therefore, the CPU can proceed to the next step without waiting for write to complete. The bus interface unit sends the address sent from the CPU to the address ___ bus. Then, when the WR signal is "L", the bus interface unit sends the data in the data buffer to the data bus and writes it to memory.
BUS CYCLE
The M37754M8C-XXXGP can select bus cycles shown in Figures 6 and 7. Central processing unit (CPU) running speed can be selected from low-speed running (clock 1 12.5 MHz) and high-speed running (clock 1 20 MHz); it is selected by bit 3 of processor mode register 1 (see Figure 9). When accessing the external memory, the bus cycle is selected by bits 4 and 5 of processor mode register 1. When accessing the internal memory, the bus cycle is selected by bit 2 of processor mode register 0 (see Figure 14). Figure 8 shows output signals at 3- access in high-speed running. ___ The BHE signal___ becomes "L" when accessing the odd address. Signals A0 and BHE indicate the differences between 1-byte read in even address, 1-byte read in odd address, and simultaneous 2-byte read in even and odd address; these signals also indicate the differrences between 1-byte write in even address, 1-byte write in odd address, and simultaneous 2-byte write in even and odd address. The A0 signal, which is bit 0 of address, becomes "L" when accessing an even address.
___
Table 1. Signals A0 and BHE Access method Simultaneous Access of 1 byte Access of 1 byte Signal access of 2 bytes in even address in odd address A0 "L" "L" "H" ___ BHE "L" "H" "L"
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Low-speed running (1 12.5 MHZ) Internal memory access 2- access
Read RD WR Ai Di 1bus cycle = 2 ADRS RD WR Ai Di ADRS W-D 1bus cycle = 2 Write RD WR Ai Di ADRS R-D 1bus cycle = 2
External memory access 2- access
Read RD WR Ai Di ADRS W-D 1bus cycle = 2 Write
3- access
Read RD WR Ai Di ADRS R-D 1bus cycle = 3 RD WR Ai Di ADRS W-D 1bus cycle = 3 Write
------------------------------
4- access
Read Write RD WR RD WR
ADRS : Address R-D : Read data W-D : Write data
Ai Di
ADRS R-D 1bus cycle = 4
Ai Di
ADRS W-D 1bus cycle = 4
Fig. 6 Bus cycle selection (low-speed running)
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
High-speed running (1 20 MHZ) Internal memory access 2- access (Note)
Read RD WR Ai Di 1bus cycle = 2 ADRS RD WR Ai Di ADRS W-D 1bus cycle = 2 Write RD WR Ai Di ADRS R-D 1bus cycle = 3
External memory access 3- access
Read RD WR Ai Di ADRS W-D 1bus cycle = 3 Write
3- access (Note)
Read RD WR Ai Di 1bus cycle = 3 ADRS RD WR Ai Di ADRS W-D 1bus cycle = 3 Write
4- access
Read RD WR Ai Di ADRS R-D 1bus cycle = 4 RD WR Ai Di ADRS W-D 1bus cycle = 4 Write
5- access
Read RD WR Ai ADRS R-D 1bus cycle = 5 RD WR Ai Di ADRS W-D 1bus cycle = 5 Write
Note: Refer to internal memory access bus cycle select bit (bit 2 of processor mode register 0 ; Figure 14). ADRS : Address R-D : Read data W-D : Write data Fig. 7 Bus cycle selection (high-speed running)
Di
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access from even address
1 1 A0 - A23 D0 - D7 Ai Di BHE ALE
Access from odd address
1-byte Read/Write
Ai Di BHE ALE RD, WR
A0 - A23 D0 - D7
External data bus width = 8 bits
RD, WR
1
1 A0 - A23 D0 - D7 A0 - A23 D0 - D7 Ai Di BHE ALE RD, WR A0 - A23 D0 - D7 A0 - A23 D0 - D7
2-byte Read/Write
Ai Di BHE ALE RD, WR
1 Ai A0 - A19 (Note 1)
1 Ai DHi D0 - D7 DLi BHE ALE RD, WR 1 A0 - A23 D8 - D15 D0 - D7 Ai DHi DLi BHE A0 - A23 D8 - D15 (Note 1) A0 - A23 (Note 1) A0 - A23 D8 - D15 (Note 1)
1-byte Read/Write
DHi DLi BHE ALE RD, WR
External data bus width = 16 bits
1 Ai
2-byte Read/Write
DHi DLi BHE ALE RD, WR
D0 - D7
ALE RD, WR
Notes 1: It becomes Hi-Z when reading, and it outputs undefined data when writing. 2: When the external data bus width is 8 bits, the function to output the low-order address from the Di pin while RD or WR is "H" can be selected only in special area access cycle. Refer to the section on the processor mode for details.
Fig. 8 Output signals at 3- access in high-speed running
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M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7 0
6
5
4
3
2
1 0
0 0
Address
Processor mode register 1 5F16 These bits must be "00." Clock source for peripheral devices select bit (Note) 0 : 1/2 1 :1 CPU running speed select bit 0 : High-speed running 1 : Low-speed running Bus cycle select bits In high-speed running 00 : 5- access in high-speed running 01 : 4- access in high-speed running 10 : 3- access in high-speed running 11 : Do not select. In low-speed running 00 : Do not select. 01 : 4- access in low-speed running 10 : 3- access in low-speed running 11 : 2- access in low-speed running Clock source select bit 0 : 1 = f(XIN)/2 1 : 1 = f(XIN) This bit must be "0."
Note: When 1 > 12.5 MHz, set bit 2 to "0."
Fig. 9 Processor mode register 1 bit configuration
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt vector addresses. Reset is also treated as a type of interrupt and is discussed in this section, too. ___ DBC is an interrupt used during debugging. ___ Interrupts other than reset, DBC, watchdog timer, zero divide, and BRK instruction all have interrupt control registers. Table 3 shows the addresses of the interrupt control registers and Figure 10 shows the bit configuration of the interrupt control register. The interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. Also, interrupt request ___ bits other than DBC and watchdog timer can be cleared by software. ____ ___ INT4 to INT0 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected with the level/edge select bit. Furthermore, the polarity of the interrupt input can be selected with the polarity select bit. ___ ___ __ __ __ In __ INT3 external interrupt, the INT3 input, KI3 to KI0 inputs, or KI4 the ____ to KI0 inputs can be selected with bits 7 and 6 of INT3 interrupt control register. Timer and UART interrupts are described in the respective section. The priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 11. The hardware priority is fixed as the following: ___ reset > DBC > watchdog timer > other interrupts
Table 2. Interrupt types and the interrupt vector addresses Interrupts INT4 external interrupt ____ INT3 external interrupt A-D UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 ____ INT2 external interrupt ____ INT1 external interrupt ____ INT0 external interrupt Watchdog timer ____ DBC (Do not select.) Break instruction Zero divide Reset
____
Vector addresses 00FFD216 00FFD316 00FFD416 00FFD516 00FFD616 00FFD716 00FFD816 00FFD916 00FFDA16 00FFDB16 00FFDC16 00FFDD16 00FFDE16 00FFDF16 00FFE016 00FFE116 00FFE216 00FFE316 00FFE416 00FFE516 00FFE616 00FFE716 00FFE816 00FFE916 00FFEA16 00FFEB16 00FFEC16 00FFED16 00FFEE16 00FFEF16 00FFF016 00FFF116 00FFF216 00FFF316 00FFF416 00FFF516 00FFF616 00FFF716 00FFF816 00FFF916 00FFFA16 00FFFB16 00FFFC16 00FFFD16 00FFFE16 00FFFF16
7
6
5
4
3
2
1
0 Interrupt priority level Interrupt request bit (Note 1) 0 : No interrupt 1 : Interrupt
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2. Note 1: The A-D conversion interrupt request bit becomes undefined after reset. Clear this bit to "0" before use of the A-D conversion interrupt. 7 6 5 4 3 2 1 0 Interrupt priority level Interrupt request bit 0 : No interrupt 1 : Interrupt Polarity select bit 0 : Set interrupt request bit at "H" level for level sense and when changing from "H" to "L" level for edge sense. 1 : Set interrupt request bit at "L" level for level sense and when changing from "L" to "H" level for edge sense. Level/Edge select bit 0 : Edge sense 1 : Level sense Key input interrupt select bits 1, 0 (only for INT3 interrupt control register) 0 0 : INT3 interrupt selected 0 1 : Do not select. 1 0 : Key input interrupt (KI3 to KI0) selected 1 1 : Key input interrupt (KI4 to KI0) selected Interrupt control register configuration for INT4- INT0 (Note 2). Note 2: The contents of INT4 interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see Figure 15) is set to "1."
Fig. 10 Interrupt control register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 3. Addresses of interrupt control registers Interrupt control registers INT4 interrupt control register ____ INT3 interrupt control register A-D interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register ____ INT0 interrupt control register ____ INT1 interrupt control register ____ INT2 interrupt control register
____
Addresses 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C16 00007D16 00007E16 00007F16
The interrupt request bit and the interrupt priority level of each interrupt source are sampled and latched at each operation code fetch cycle while BIU is "H". However, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. The detection of an interrupt which has the highest priority is performed during that time.
Priority is determined by hardware 4 3 Watchdog timer A-D converter, UART, etc. interrupts Priority can be changed with software inside 4 2 DBC 1 Reset
Fig. 11 Interrupt priority
Level 0 INT4 INT3 A-D Interrupt request UART1 transmit UART1 receive UART0 transmit UART0 receive Reset Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Watchdog timer Timer A2 Timer A1 Timer A0 INT2 Interrupt disable flag I INT1 IPL INT0
Interrupts caused by a BRK instruction and when dividing by zero are software interrupts and are not included in this list. Other interrupts previously mentioned are A-D converter, UART, etc. interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by software. Figure 12 shows a diagram of the interrupt priority detection circuit When an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority. This comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. Finally the selected interrupt is compared with the processor interrupt priority level (IPL) contained in the processor status register (PS) and the request is accepted if it is higher than IPL and the interrupt disable ___ flag I is "0". The request is not accepted if flag I is "1". The reset, DBC, and watchdog timer interrupts are not affected by the interrupt disable flag I. When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable flag I is set to "1". Furthermore, the interrupt request bit of the accepted interrupt is cleared to "0" and the processor interrupt priority level (IPL) in the processor status register (PS) is replaced by the priority level of the accepted interrupt. Therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag I to "0" and enable further interrupts. ___ For reset, DBC, watchdog timer, zero divide, and BRK instruction interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 4.
DBC
Fig. 12 Interrupt priority detection
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
As shown in Figure 13, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been completed. The time is selected with bits 4 and 5 of the processor mode register 0 (address 5E16) shown in Figure 14. Table 5 shows the relationship between these bits and the number of cycles. After a reset, the processor mode register 0 is initialized to "0016." Therefore, the longest time is automatically set, however, the shortest time must be selected by software.
Table 4. Value set in processor interrupt level (IPL) during an interrupt Interrupt types Reset ____ DBC Watchdog timer Zero divide BRK instruction Setting value 0 7 7 Not change value of IPL. Not change value of IPL.
Table 5. Relationship between interrupt priority detection time select bit and number of cycles Priority detection time select bit Bit 5 Bit 4 0 0 0 1 1 0 Number of cycles 7 cycles of BIU 4 cycles of BIU 2 cycles of BIU
BIU
Operation code fetch cycle
Sampling pulse 0 1 2
Priority detection time Select one from 0 to 2 with bits 4 and 5 of processor mode register 0
Fig. 13 Interrupt priority detection time
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6 0
5
4
3
2
1
0 Processor mode register 0 (5E16) Processor mode bits 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Do not select. Internal memory access bus cycle select bit (Note) Internal memory access condition in high-speed running 0 : 2- access for internal RAM, 3- access for internal ROM and SFR 1 : 2- access for internal RAM, internal ROM, SFR Software reset bit The microcomputer is reset when this bit is set to "1". Interrupt priority detection time select bit 0 0 : Select 0 in Figure 13 0 1 : Select 1 in Figure 13 1 0 : Select 2 in Figure 13 Test mode bit This bit must be "0." Clock 1 output select bit 0 : No 1 output 1 : 1 output
Note: When selecting low-speed running, set bit 2 to "0."
Fig. 14 Processor mode register 0 bit configuration
7 6 5 4 3 2 1 0 Particular function select register 1 (6D16) Transmit clock output pin select bit 00 : Normal mode (output only to CLK0) 01 : Plural clocks specified; output to CLK0 10 : Plural clocks specified; output to CLKS0 11 : Plural clocks specified; output to CLKS1 Internal clock stop select bit at WIT (Note 1) 0 : Clock for peripheral function and watchdog timer are operating at WIT 1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT Watchdog timer's clock select bit (Note 1) 0 : Exclusive clock deviding circuit output (Wf512, Wf32) is used as clock for watchdog timer. Clock (Wf512, Wf32) for watchdog timer does not change in hold. 1 : Clock for peripheral device deviding circuit output (Pf512, Pf32) is used as clock for watchdog timer. Clock (Pf512, Pf32) for watchdog timer changes in hold. Watchdog timer exclusive clock dividing circuit is stopped. Signal output stop select bit (Note 1) Refer to Table 8. Expansion function select bit (Note 2) Refer to Figure 62. Pull-up select bit 0 (Note 3) 0 : With no pull-up for P57, P56, P55, P54 1 : With pull-up for P57, P56, P55, P54 Pull-up select bit 1 (Note 3) 0 : With no pull-up for P95 1 : With pull-up for P95
TC1 TC0
Notes 1: Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to "1." 2: After bit 5 is set to "1" once, bit 5 cannot be cleared to "0" except external reset and software reset. 3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0-7.
Fig. 15 Processor mode register 0 bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
__
___
The INT3 interrupt___ function as the key input interrupt by setting can bits 7 and 6 of the INT3__ interrupt control register. The key input inter__ __ __ rupt uses inputs KI3 to KI0 or inputs KI4 to KI0. Figure 10 shows the interrupt control register bit configuration. Figure 15 shows the particular function select register 1 bit configuration, and Figure 16 ___ shows the ___ INT3/key input interrupt input circuit block diagram. When the INT3 interrupt control register's bit 7 is___and its bit 6 is "0" ___ "0", a signal from the INT3 pin is connected to the INT3 interrupt con___ trol circuit and INT3 external interrupt is normally performed. ___ When the INT3 interrupt control register's bit 7 is "1" and its bit 6 is __ __ "0", signals from the KI3 to KI0 pins, which correspond to ports P57 to P54, are inverted and then the logical sum of these signals is con___ nected to the INT3 interrupt control circuit. In this case, the external __ __ interrupt which uses the KI3 to KI0 pins is performed. ___ When the INT3 interrupt control register's bit 7 is "1" and its bit 6 is __ __ "1", signals from the KI4 pin, which corresponds to port P95, KI3 to __ KI0 pins, which correspond to ports P57 to P54, are inverted and then ___ the logical sum of these signals is connected to the INT3 interrupt __ control circuit. In this case, the external interrupt which uses the KI4
to KI0 pins is performed. When using the above key input interrupt, select the edge sense ___ which uses the falling edge from "H" to "L" with the INT3 interrupt control register so that an interrupt request can occur by inputting "L" __ __ __ __ to each of the KI3 to KI0 pins or the KI4 to KI0 pins. The interrupt vec___ tor is common to the INT3 interrupt's one. Additionally, pull-up resis__ __ tor (transistors) can be added to the KI4 to KI0 pins by setting the contents of the particular function select register 1's bits 7 and 6 and setting "0" to each bit of the corresponding port's direction register.
INT3 interrupt control register Pull-up select bit 1 Port P95 direction register P95/INT3/KI4 Key input interrupt select bit 1 Bit 7 of INT3 interrupt control register 0 Pull-up transistor P57/TA3IN/KI3 Pull-up select bit 0 Port P57 direction register Interrupt control circuit 1
(Address 6F16)
When the key input interrupt is selected, select the edge sense which uses falling edge from "H" to "L".
Key input interrupt select bit 0 (Bit 6 of INT3 interrupt control register)
INT3 interrupt request
Pull-up transistor P56/TA3OUT/KI2 Pull-up transistor P55/TA2IN/KI1 Pull-up transistor P54/TA2OUT/KI0
Port P56 direction register
Port P55 direction register
Port P54 direction register
___
Fig. 16 INT3/key input interrupt input circuit block diagram
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER
There are eight 16-bit timers. They are divided by type into timer A(5) and timer B(3). The timer I/O pins are multiplexed with I/O pins for port P5 and P6. To use these pins as timer input pins, the data direction register bit corresponding to the pin must be cleared to "0" to specify input mode.
(1) Timer mode [00]
Figure 18 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0 and 1 of the timer Ai mode register must be "0" in timer mode. Bits 3, 4, and 5 are used to select the gate function. Bits 4 and 5 must be "0" when not selecting the gate function. Bit 3 is ignored if bit 4 is "0". Bits 6 and 7 are used to select the timer counter source. The counting of the selected clock starts when the count start bit is "1" and stops when it is "0". Figure 19 shows the bit configuration of the count start bit. The counter is decremented, an interrupt is caused and the interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is transferred to the counter and count is continued. When data is written to timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency dividing ratio is 1/(n+1).
TIMER A
Figure 17 shows a block diagram of timer A. Timer A has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each of these modes is described below.
Data bus (odd)
Data bus (even) Clock source selection Pf2 Pf16 Pf64 Pf512 Timer(gate function) Counter(16) Polarity selection Event counter Count start bit (4016) External trigger Down count Up/Down Always decremented except in event count mode Addresses Timer A0 4716 4616 Timer A1 4916 4816 Timer A2 4B16 4A16 Timer A3 4D16 4C16 Timer A4 4F16 4E16 Up-down bit (4416) Pulse output Toggle flip-flop TAiOUT (i = 0-4) * Timer * One-shot * Pulse width modulation (Lower 8 bits) Reload register(16) (Higher 8 bits)
TAiIN (i = 0-4)
Note: Perform write and read to/from timer Ai register in the condition of 16-bit data length : data length flag (m) = "0".
Fig. 17 Block diagram of timer A
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse output function
When bit 2 of the timer Ai mode register is "1", the output is generated from TAiOUT pin. The output is toggled each time the contents of the counter reaches to 000016. When the contents of the count start bit is "0", "L" is output from TAiOUT pin. When bit 2 is "0", TAiOUT can be used as a normal port pin. When bit 4 is "0", TAiIN can be used as a normal port pin.
Gate function
When bit 4 is "1", counting is performed only while the input signal from the TAiIN pin is "H" or "L" as shown in Figure 20. Therefore, this can be used to measure the pulse width of the TAiIN input signal. Whether to count while the input signal is "H" or while it is "L" is determined by bit 3. If bit 3 is "1", counting is performed while the TAiIN pin input signal is "H" and if bit 3 is "0", counting is performed while it is "L".
When bit 5 is "0, counting restarts from the value which is contained at restarting (gate function 0 [no reload]) and an overflow occurs (n + 1) cycles of the count source later. Figure 21 shows that operation. When bit 5 is "1", counting restarts from the value which is obtained by reload at restarting (gate function 1 [reload]) and the first overflow occurs (n + 2) cycles of the count source later. Figure 22 shows that operation. After that, while the input signal from the TAiIN pin keeps valid level, an overflow occurs at (n + 1)- cycle intervals. Make sure to set the value of 1 or more to n. When gate functions are used, the duration of "H" or "L" on the TAiIN pin must be 2 or more cycles of the timer count source.
7
6
5
4
3
2
1 0
0 0
Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register
Addresses 5616 5716 5816 5916 5A16
0 0 : Always "00" in timer mode 0 : No pulse output (TAiOUT is normal port pin) 1 : Pulse output 0 x : No gate function (TAiIN is normal port pin) 1 0 : Count only while TAiIN input is "L" 1 1 : Count only while TAiIN input is "H" 0 : Gate function 0 (No reload) 1 : Gate function 1 (Reload) ; Note Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512 Note: When selecting no gate function (bit 4 = "0") in timer mode, fix bit 5 to "0".
Fig. 18 Timer Ai mode register bit configuration during timer mode
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 Count start register (Stop at "0", Start at "1") Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Address 4016
Fig. 19 Count start flag bit configuration
Selected clock source Pfi
TAiIN
Timer mode register Bit 4 1 Bit 3 0
Timer mode register Bit 4 1 Bit 3 1
Fig. 20 Count waveform when gate function is available
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FFFF16 n Count start
Count stop Count stop Overflow
Count start flag Input level to TAiIN pin TAi interrupt request bit
"1" "0" Valid level Invalid level
Time
Cleared by accepting the interrupt request or by software
Fig. 21 Timer operation example with gate function 0 (no reload) selected
FFFF16 n Count start
Reloaded Reloaded duration Count stop Overflow
Count start flag Input level to TAiIN pin TAi interrupt request bit
"1" "0" Valid level Invalid level
Time
Cleared by accepting the interrupt request or by software
Fig. 22 Timer operation example with gate function 1 (reload) selected
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 23 shows the bit configuration of the timer Ai mode register during event counter mode. In event counter mode, bit 0 of the timer Ai mode register must be "1" and bits 1 and 5 must be "0". The input signal from the TAiIN pin is counted when the count start bit shown in Figure 19 is "1" and counting is stopped when it is "0". Count is performed at the fall of the input signal when bit 3 is "0" and at the rise of the signal when it is "1". In event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the TAiOUT pin. When bit 4 of the timer Ai mode register is "0", the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is "0" and increment when it is "1"). Figure 24 shows the bit configuration of the up-down register. When bit 4 of the timer Ai mode register is "1", the input signal from the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be "0" if bit 4 is "1." It is because if bit 2 is "1", TAiOUT pin becomes an output pin to output pulses. The count is decremented when the input signal from the TAiOUT pin is "L" and incremented when it is "H". Determine the level of the input signal from the TAiOUT pin before a valid edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 000016 (decrement count) or FFFF16 (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. When bit 2 is "1," each time the counter reaches 000016 (decrement count) or FFFF16(increment count), the waveform's polarity is reversed and is output from TAiOUT pin. If bit 2 is "0", TAiOUT pin can be used as a normal port pin. However, if bit 4 is "1" and the TAiOUT pin is used as an output pin, the output from the pin changes the count direction. Therefore, bit 4 must be "0" unless the output from the TAiOUT pin is to be used to select the count direction.
Addresses 5616 5716 5816 5916 5A16
76543210 x x0 01
Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register
0 1 : Always "01" in event counter mode 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal
0 : Increment or decrement according to up/down flag 1 : Increment or decrement according to TAiOUT pin input signal level
0 : Always "0" in event counter mode x x : Not used in event counter mode
Fig. 23
Timer Ai mode register bit configuration during event counter mode
76543210 Up-down register Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit
Address 4416
Timer A2 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode
Fig. 24 Up-down register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time.
Two-phase pulse processing
In event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer A2, A3, or A4. There are two types of two-phase pulse processing operations. One uses timers A2 and A3, and the other uses timer A4. In both processing operations, two pulses described above are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively. When timers A2 and A3 are used, as shown in Figure 25, the count is incremented when a rising edge is input to the TAkIN pin after the level of TAkOUT(k=2,3) pin changes from "L" to "H", and when the falling edge is input, the count is decremented. For timer A4, as shown in Figure 26, when a phase-related pulse with a rising edge input to the TA4IN pin is input after the level of TA4OUT pin changes from "L" to "H", the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase-related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from "H" to "L", the count is decremented at the respective rising edge and falling edge of the TA4IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, timer Aj mode register bit 0 and bit 4 must
be set to "1" and bits 1, 2, 3, and 5 must be "0". Bits 6 and 7 are ignored. Note that bits 5, 6, and 7 of the up-down register (4416) are the two-phase pulse signal processing select bits for timers A2, A3 and A4 respectively. Each timer operates in normal event counter mode when the corresponding bit is "0" and performs two-phase pulse signal processing when it is "1". Count is started by setting the count start bit to "1". Data write and read are performed in the same way as for normal event counter mode. Note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. Also, there can be no pulse output in this mode.
76543210 x x010001
Timer A2 mode register Timer A3 mode register Timer A4 mode register
Addresses 5816 5916 5A16
0 1 : Always "01" in event counter mode 0 1 0 0 : Always "0100" when processing two-phase pulse signal x x : Not used in event counter mode
Fig. 27 Timer Aj mode register bit configuration when performing two-phase pulse signal processing in event counter mode
TAkOUT
TAkIN
(k = 2, 3)
Incrementcount
Incrementcount
Incrementcount
Decrementcount
Decrementcount
Decrementcount
Fig. 25 Two-phase pulse processing operation of timers A2 and timer A3
TA4OUT Increment-count at each edge Decrement-count at each edge
TA4IN Increment-count at each edge Decrement-count at each edge
Fig. 26 Two-phase pulse processing operation of timer A4
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 28 shows the bit configuration of the timer Ai mode register during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5 must be "0" and bit 1 and bit 2 must be "1". The trigger is enabled when the count start bit is "1". The trigger can be generated by software or it can be input from the TAiIN pin. Software trigger is selected when bit 4 is "0" and the input signal from the TAiIN pin is used as the trigger when it is "1". Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise of the trigger signal when it is "1". Software trigger is generated by setting the bit in the one-shot start bit corresponding to each timer. Figure 29 shows the bit configuration of the one-shot start register. As shown in Figure 30, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. If the contents of the counter is not 000016, the TAiOUT pin goes "H" when a trigger signal is received. The count direction is decrement. When the counter reaches 000116, The TAiOUT pin goes "L" and count is stopped. The contents of the reload register is transferred to the counter. At the same time, an interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set. This is repeated each time a trigger signal is received. The output pulse width is 1 pulse frequency of the selected clock x (counter's value at the time of trigger). If the count start flag is "0", TAiOUT goes "L". Therefore, the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start bit. As shown in Figure 31, a trigger signal can be received before the operation for the previous trigger signal is completed. In this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. Except when retriggering while operating, the contents of the reload register is not transferred to the counter by triggering. When retriggering, there must be at least one timer count source cycle before a new trigger can be issued. Data write is performed in the same way as for timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. Undefined data is read when timer Ai is read.
76543210 0 110
Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register
Addresses 5616 5716 5816 5916 5A16
1 0 : Always "10" in one-shot pulse mode 1 : Always "1" in one-shot pulse mode 0 x : Software trigger 1 0 : Trigger at the falling edge of TAiIN input 1 1 : Trigger at the rising edge of TAiIN input 0 : Always "0" in one-shot pulse mode Clock source select 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512
Fig. 28 Timer Ai mode register bit configuration during one-shot pulse mode
76543210 One-shot start register
Address 4216
Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit
Fig. 29 One-shot start register bit configuration
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M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selected clock source Pfi
TAiIN (rising edge)
TAiOUT
Example when the contents of the reload register is 000316
Fig. 30 Pulse output example when external rising edge is selected
Selected clock source Pfi
TAiIN (rising edge)
TAiOUT
Example when the contents of the reload register is 000416
Fig. 31 Example when trigger is re-issued during pulse output
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation mode [11]
Figure 32 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to "1". Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is "0" and 8-bit length pulse width modulator is selected when it is "1". The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAiIN pin (external trigger). The software trigger mode is selected when bit 4 is "0". Pulse width modulator is started and a pulse is output from TAiOUT when the timer Ai start bit is set to "1". The external trigger mode is selected when bit 4 is "1". Pulse width modulation starts when a trigger signal is input from the TAiIN pin when the timer Ai start bit is "1". Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise when it is "1". When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the timer Ai start bit is set to "1" and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 33 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration "H" of pulse is 1 xm selected clock frequency and the output pulse period is 1 x (216 -1). selected clock frequency An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is "1". The reload register and the counter are both divided into 8-bit halves. The low-order 8 bits function as a prescaler and the high-order 8 bits
function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6 and 7. A pulse is generated when the counter reaches 000016 as shown in Figure 34. At the same time, the contents of the reload register is transferred to the counter and count is continued.
76543210 111
Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register
Addresses 5616 5716 5816 5916 5A16
1 1 : Always "11" in pulse width modulation mode 1 : Always "1" in pulse width modulation mode 0 x : Software trigger 1 0 : Trigger at the falling of TAiIN input 1 1 : Trigger at the rising of TAiIN input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512
Fig. 32 Timer Ai mode register bit configuration during pulse width modulation mode
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Therefore, if the low-order 8 bits of the reload register are n, the period of the generated pulse is 1 x (n+1). selected clock frequency The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the
high-order 8 bits of the reload register are m, the duration "H" of pulse is 1 x (n+1) x m. selected clock frequency
And the output pulse period is 1 selected clock frequency
x (n+1) x (28-1).
1/Pfi x (216 - 1)
Selected clock source Pfi
TAiIN (rising edge) This trigger is not accepted 1/Pfi x (m)
TAiOUT
Example when the contents of the reload register is 000316
Fig. 33 16-bit length pulse width modulator output pulse example
1/Pfi x (n + 1) x (28 - 1)
Selected clock source Pfi
TAiIN (falling edge) 1/Pfi x (n + 1) Prescaler output (when n = 2)
1/Pfi x (n + 1) x (m) 8-bit length pulse width modulator output (when m = 2)
Fig. 34 8-bit length pulse width modulator output pulse example
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
Figure 35 shows a block diagram of timer B. Timer B has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. The mode is selected with bits 0 and 1 of the timer Bi mode register (i=0 to 2). Each of these modes is described below.
(1) Timer mode [00]
Figure 36 shows the bit configuration of the timer Bi mode register during timer mode. Bits 0 and 1 of the timer Bi mode register must always be "0" in timer mode. Bits 6 and 7 are used to select the clock source. The counting of the selected clock starts when the count start bit is "1" and stops when "0".
As shown in Figure 19, the timer Bi count start bit is at the same address as the timer Ai count start bit. The count is decremented, an interrupt occurs, and the interrupt request bit in the timer Bi interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register is stored in the counter and count is continued. Timer Bi does not have a pulse output function or a gate function like timer A. When data is written to timer Bi halted, it is written to the reload register and the counter. When data is written to timer Bi which is busy, the data is written to the reload register, but not to the counter. The new data is reloaded from the reload register to the counter at the next reload time and counting continues. The contents of the counter can be read at any time.
Data bus (odd)
Data bus (even) Clock source selection Pf2 Pf16 Pf64 Pf512 Counter (16) TBiIN (i = 0 - 2) Polarity selection and edge pulse generator Event counter Count start bit (4016) Addresses Timer B0 5116 5016 Timer B1 5316 5216 Timer B2 5516 5416 (Lower 8 bits) Reload register (16) (Higher 8 bits)
* Timer * Pulse period measurement/Pulse width measurement
Counter reset circuit
Note: Perform write and read to/from timer Bi register in the condition of 16-bit data length : data length flag (m) ="0".
Fig. 35 Timer B block diagram
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MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 37 shows the bit configuration of the timer Bi mode register during event counter mode. In event counter mode, bit 0 in the timer Bi mode register must be "1" and bit 1 must be "0". The input signal from the TBiIN pin is counted when the count start flag is "1" and counting is stopped when it is "0". Count is performed at the fall of the input signal when bits 2, and 3 are "0" and at the rise of the input signal when bit 3 is "0" and bit 2 is "1". When bit 3 is "1" and bit 2 is "0", count is performed at the rise and fall of the input signal. Data write, data read and timer interrupt are performed in the same way as for timer mode.
Timer B0 mode register Timer B1 mode register 76543210 x xx00 Timer B2 mode register 0 0 : Always "00" in timer mode x x : Not used in timer mode and may be any Not used in timer mode Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512 Addresses 5B16 5C16 5D16
(3) Pulse period measurement/pulse width measurement mode [10]
Figure 38 shows the bit configuration of the timer Bi mode register during pulse period measurement/pulse width measurement mode. In pulse period measurement/pulse width measurement mode, bit 0 must be "0" and bit 1 must be "1". Bits 6 and 7 are used to select the clock source. The selected clock is counted when the count start flag is "1" and counting stops when it is "0". The pulse period measurement mode is selected when bit 3 is "0". In pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBiIN pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. In this case, the reload register acts as a buffer register. When bit 2 is "0", the clock is counted from the fall of the input signal to the next fall. When bit 2 is "1", the clock is counted from the rise of the input signal to the next rise. In the case of counting from the fall of the input signal to the next fall, counting is performed as follows. As shown in Figure 39, when the fall of the input signal from TBiIN pin is detected, the contents of the counter is transferred to the reload register. Next the counter is cleared and count is started from the next clock. When the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and the count is started. The period from the fall of the input signal to the next fall is measured in this way. After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer Bi interrupt control register is set. However, no interrupt request signal is generated when the contents of the counter is transferred first to the reload register after the count start bit is set to "1". When bit 3 is "1", the pulse width measurement mode is selected. Pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the TBiIN pin input signal to the next rise or from the rise of the input signal to the next fall as shown in Figure 40.
Fig. 36 Timer Bi mode register bit configuration during timer mode
Timer B0 mode register Timer B1 mode register 76543210 xxx 01 Timer B2 mode register
Addresses 5B16 5C16 5D16
0 1 : Always "01" in event counter mode 0 0 : Count at the falling edge of input signal 0 1 : Count at the rising edge of input signal 1 0 : Count at the both falling edge and rising edge of input signal x x x : Not used in event counter mode
Fig. 37
Timer Bi mode register bit configuration during event counter mode
Timer B0 mode register Timer B1 mode register 76543210 10 Timer B2 mode register
Addresses 5B16 5C16 5D16
1 0 : Always "10" in pulse period measurement/pulse width measurement mode 0 0 : Count from the falling edge of input signal to the next falling one 0 1 : Count from the rising edge of input signal to the next rising one 1 0 : Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one Timer Bi overflow flag Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512
Fig. 38 Timer Bi mode register bit configuration during pulse period measurement/pulse width measurement mode
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When timer Bi is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to "1" when the timer Bi counter reaches 000016, which indicates that a pulse width or pulse period is longer than that which can be measured by a 16-bit length. This flag is cleared by writing data to the corresponding timer Bi mode register. This bit is set to "1"at reset.
Selected clock source Pfi
TBiIN
Reload register counter
Counter 0
Count start flag
Interrupt request signal
Fig. 39 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one)
Selected clock source Pfi
TBiIN
Reload register counter
Counter 0
Count start flag
Interrupt request signal
Fig. 40 Pulse width measurement mode operation
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer function for motor control
Three-phase motor drive waveform and pulse motor drive waveform can be output by using plural internal timers A and B. Those modes are explained bellow.
7
6
5 x
4
3
2 1
1 0
0 0
Waveform output mode register Waveform output select bits 100 : Fix to "100" in three-phase waveform mode
Address 1A16
Three-phase motor drive waveform output mode (three-phase waveform mode)
Three-phase waveform mode using four timers of the timers A0, A1, A2 and B4 is selected by setting the waveform output select bits of the waveform output mode register (address 1A16, Figure 41) to "1002". There are two types of the three-phase waveform mode: threephase mode 0 and three-phase mode 1. Bit 4 of the waveform output mode register selects either mode. In three-phase waveform mode, set the corresponding timer mode registers of timers A0, A1, and A2 to select the one-shot pulse mode with the rising edge of external trigger; set the timer mode register of timer B2 to select the timer mode. Figure 43 shows the three-phase waveform mode block diagram. The three-phase waveform mode outputs six waveforms, positive _ _ __ waveforms (U, V, W phases) and negative waveforms (U, V, W phases), from the respective ports with "L" level active. _ _ Timer A2 controls U and U phases; timer A1 does V and V phases __ and timer A0 does W and W phases. Timer B2 controls those oneshot pulses' period of timers A2, A1 and A0. In the waveform output, a short circuit prevention time can be set to prevent "L" level of positive waveforms (U, V, W phases) from over_ _ __ lapping with "L" level of their negative waveforms (U, V, W phases). The short circuit prevention time can be set with three 8-bit deadtime timers, sharing one reload register. The dead-time timer operates as a one-shot timer. As its start trigger, both the rising and falling edges of timers A0 to A2's one-shot pulses or their falling edge. Bit 6 of the waveform output mode register selects it. When that is "0", both the rising and falling edges become the start trigger; when that is "1", the falling edge becomes it.
(Valid in three-phase mode 1) Three-phase output polarity set buffer 0 : "H" output 1 : "L" output Three-phase mode select bit 0 : Three-phase mode 0 1 : Three-phase mode 1 Not used in three-phase waveform mode Dead-time timer trigger select bit 0 : Both edge of one-shot pulse with timers A2 to A0 1 : Only the falling edge of one-shot pulse with timers A2 to A0 Waveform output control bit 0 : Waveform output disabled 1 : Waveform output enabled Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", this register's contents can be changed from the status during reset (in Fig.76).
Fig. 41 Waveform output mode register bit configuration
7
6
5 0
4 1
3 1
2
1 1
0 0
Address Timer A0 mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816
Fix to "10" in three-phase waveform mode Fix to "1" in timers A0, A1 in timer A2 0 : No one-shot pulse output 1 : One-shot pulse output Fix to "011" in three-phase waveform mode Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512 7 6 5 x 4 3 x 2 x 1 0 0 0 Address 5D16
Timer B2 mode register
Fix to "00" in three-phase waveform mode Not used in three-phase waveform mode Clock source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512
Fig. 42 Timer A0, A1, A2, mode register and timer B2 mode register bit configuration
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Interrupt request interval set bit DQ Reset R Interval control "1" Timer B2 interrupt request signal DQ "0" Reset Reload register Waveform output control bit DQ INT0 T Dead-time timer (8) Reset R Dead-time timer clock source select bit Pf2 Pf4 Pf8 TR
PR
Interrupt validity DQ output select bit R
IN LIM E
Three-phase output polarity set buffer
A
Timer B2
e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som
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(Timer mode)
Timer A2
Reload
Timer A21
T
Timer A2 counter (One-shot pulse mode) "0" DQ
"H" output of U-phase fix buffer Output polarity set toggle flipflop 2
Fig. 43 Three-phase waveform mode block diagram
SQ T RQ DQ T R DQ R TR DQ T DQ V TR DQ U "1"
"H" output of U-phase fix buffer
U-phase output polarity DQ set buffer
Timer A1
Reload
Timer A11
T
Timer A1 counter
s Dead-time timer (8)
"0"
"H" output of V-phase fix buffer
(One-shot pulse mode)
Output polarity set toggle flipflop 1
V-phase output polarity D Q set buffer DQ R DQ R "1"
SQ T RQ DQ TR DQ TR
DQ T
W
Timer A0
Reload
Timer A01
"H" output of V-phase fix buffer
DQ T
U
T
Timer A0 counter (One-shot pulse mode) "0"
Output polarity set toggle flipflop 0
s Dead-time timer (8)
W-phase output polarity D Q set buffer "1" Q D Three-phase mode R select bit Reset
SQ T RQ
DQ
"H" output of W-phase fix buffer
DQ R DQ
"H" output of W-phase fix buffer
DQ TR DQ R TR
V T
DQ T
W
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", the following registers' contents can be changed from the status after reset (in Fig.76): Waveform output mode register (address 1A16), Dead-time timer (address 1B16), Pulse output data registers 0 and 1 (addresses 1C16, 1D16), and Timer A write register (address 4516).
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
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IN LIM E
A
RY
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When writing data to the dead-time timer (address 1B16), the data is written to the reload register shared by three dead-time timers. When the dead-time timers catch the start trigger from the respective timers, the reload register contents are transferred to its counter and the dead-time timer decrements with the clock source selected by bits 6 and 7 of pulse output data register (address 1C16). Additionally, this timer can accept another trigger before completion of the preceding trigger operation. In this case, after transferring the reload register contents to the dead-time timer at acceptance of the trigger, the value is decremented. The dead-time timer operates as a one-shot timer. Accordingly, this timer starts pulse output when the trigger is caught, and finishes pulse output and stops operation when its contents become "0016", and waits next trigger.
In the three-phase waveform mode, setting bit 7 of the waveform output mode register (address 1A16) to "1" makes positive waveforms _ _ __ (U, V, W phases) and their negative waveforms (U, V, W phases) output from the respective ports. When that bit is "0", their ports are ____ floating. That bit is cleared to "0" by inputting falling edge to the INT0 pin or reset other than clearing by an instruction.. Additionally, setting bits 5 to 3 of the pulse output data register 1 (address 1C16) to "1" makes the corresponding positive waveforms fixed to "H", and setting bits 7 to 5 of the pulse output data register 0 (address 1D16) to "1" makes the corresponding negative waveforms fixed to "H". ____ When selecting the three-phase waveform mode, INT0 pin become input-only pin.
7
6
5
4
3
2 x
1
0 Pulse output data register 1
Address 1C16
7
6
5
4
3
2 x
1 x
0 x
Pulse output data register 0
Address 1D16
V-phase output polarity set buffer (Three-phase mode 0) 0 : "H" output 1 : "L" output Interrupt request interval set bit (Three-phase mode 1) 0 : At every second time 1 : At every fourth time U-phase output polarity set buffer (Three-phase mode 0) 0 : "H" output 1 : "L" output Interrupt validity output select bit (Three-phase mode 1) 0 : Timer B2 interrupt request generated at each even-numbered underflow of timer B2. 1 : Timer B2 interrupt request generated at each odd-numbered underflow of timer B2.
! : Not used in three-phase waveform mode (Valid in three-phase mode 0) W-phase output polarity set buffer 0 : "H" output 1 : "L" output "H" output of W-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed "H" output of V-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed "H" output of U-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", these registers' contents can be changed from the status during reset (in Fig.76).
! : Not used in three-phase waveform mode "H" output of W-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed "H" output of V-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed "H" output of U-phase fix buffer 0 : Released from fixed output 1 : "H" output fixed Clock-source-of-dead-time timer select bits 00 : Pf2 selected 01 : Pf4 selected 10 : Pf8 selected 11 : Do not select.
Fig. 44 Bit configuration of pulse output data registers 1 and 0 in three-phase waveform mode
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IM REL
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Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase mode 0
In selecting three-phase waveform mode, three-phase mode 0 is selected by setting bit 4 of the waveform output mode register (address 1A16) to "0". The output polarity of three-phase waveform depends on the output polarity set toggle flip-flop. The positive waveform of the three-phase waveform is "H" output when the toggle flip-flop is "0"; it is "L" output when the toggle flip-flop is "1". (Three-phase waveform is output as a negative waveform.) Each output polarity set toggle flip-flop has the output polarity set buffer shown in Figure 44. When the timer B2's counter contents become 000016, the contents of output polarity set buffer are set into the output polarity set toggle flip-flop. After that, the polarity of the contents of output polarity set toggle flip-flop are reversed each time completion of one-shot pulse of timer (timers A2 to A0) corresponding to each phase. Figure 45 shows an example of U-phase waveform and the output operation is explained. Three-phase mode 0 becomes valid when writing "0" to the U-phase output polarity set buffer (bit 1 at address 1C16) and actuating the timer B2. When the counter of timer B2 becomes 000016, the timer B2 interrupt request signal occurs and the timer A2 simultaneously starts one-shot pulse output. At this time, the contents of U-phase output polarity set buffer, "0" in this case, are set into the output polarity set toggle flip-flop 2. When the one-shot pulse output of timer A2 is completed, the contents of output polarity set toggle flip-flop 2 is reversed from "0" to "1". Simultaneously, the one-shot pulse of the 8-bit dead-time timer is output for ensuring time not to overlap "L" levels of U phase wave_ form and its negative U phase waveform. The U-phase waveform output keeps "H" level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from "0" to "1" owing to the timer A2's one-shot pulse output. When the one-shot pulse output of the dead-time timer is completed, "1" of output polarity set toggle flip-flop 2 which has been reversed becomes valid and the U phase waveform changes to "L" level.
Then, write "1" to the U-phase output polarity set buffer (bit 1 at address 1C16) before the counter of timer B2 becomes 000016. After that, when the counter of timer B2 becomes 000016, the timer A2 starts one-shot pulse output. Simultaneously, the contents of U-phase output polarity set buffer, "1" in this case, are set into the output polarity set toggle flip-flop 2 and the U phase waveform remains "L" level. When the one-shot pulse output of timer A2 is completed, the contents of output polarity set toggle flip-flop 2 is reversed from "1" to "0". Simultaneously, the one-shot pulse output of the dead-time timer starts. When the contents of output polarity set toggle flip-flop 2 are reversed from "1" to "0", the U-phase waveform changes its output level from "L" to "H" without waiting for completion of the one-shot pulse output of the dead-time timer. U-phase waveform is generated by repeating the operation _ above. The way to generate U-phase waveform, which is the negative phase of U-phase, is the same as that for U-phase waveform except that the contents of output polarity set toggle flip-flop 2 are treated as the reversed signal from the case of U-phase waveform. _ In this way, U-phase waveform and U-phase waveform, having the negative phase of U-phase, are output from the pins so that their "L" levels do not overlap each other. The width of "L" level can be also modified by changing the value of timer B2 or timer A2. _ __ V-, W-phase waveform and V-, W-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation. The explanation above is an example of three-phase waveform generating due to an triangular wave modulation. Three-phase waveform due to a saw-tooth-wave modulation can also be generated by fixing each beginning level of phases.
Signal output each time Timer B2 becomes 000016 One-shot pulse output with timer A2 Contents of output polarity set toggle flip-flop 2
Reversed pulse output signal with dead-time timer
U-phase waveform output
U-phase waveform output
Fig. 45 U-phase waveform output example in three-phase mode 0 (triangular wave modulation)
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IN LIM E
A
RY
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase mode 1
In selecting three-phase waveform mode, three-phase mode 1 is selected by setting bit 4 of the waveform output mode register (address 1A16) to "1". In this mode, each of timers A0 to A2 can have two timer registers and the contents of those registers are alternately reloaded into the counter each time the counter of timer B2 becomes 000016. About write operation to two timer registers, when rewriting to each timer register of timers A0, A1 and A2 after writing to each timer register of them, the data is written each to timers A01, A11 and A21. When writing to each timer register, the timer A write register (in Figure 46) indicates the timer to be intended for write. The interrupt request normally occurs when the counter of timer B2 becomes 000016. However, this occurrence interval can be switched between "every second time" and "every fourth time." Bit 0 of the pulse output data register 1 (address 1C16) selects that. Additionally, "0" or "1" of the three-phase output polarity set buffer can be used as the occurrence factor of timer B2 interrupt request. Bit 1 of the pulse output data register 1 (address 1C16) selects that. When the timer B2's counter contents become 000016, the contents of three-phase output polarity set buffer are set into the output polarity set toggle flip-flop on which .the output polarity of three-phase waveform depends. The contents of three-phase output polarity set buffer are reversed after that operation. The polarity of the contents of output polarity set toggle flip-flop is reversed each time completion of one-shot pulse of timer (timers A2 to A0) corresponding to each phase. Figure 47 shows an example of U-phase waveform and the output operation is explained. Write "0" to the three-phase output polarity set buffer (bit 3 at address 1A16). Clear the interrupt request interval set bit (bit 0 at address 1C16) to "0" so that the timer B2 interrupt request may occur at every second time. Additionally, clear the interrupt validity output select bit (bit 1 at address 1C16) so that the timer B2 interrupt request may occur at "0" of the three-phase output polarity set buffer.
After the procedure above, three-phase mode 1 starts operation when actuating the timer B2. When the counter of timer B2 becomes 000016, the timer B2 interrupt request occurs and timer A2 simultaneously starts one-shot pulse output. At this time, the contents of three-phase output polarity set buffer, "0" in this case, are set into the output polarity set toggle flip-flop 2. The contents of three-phase output polarity set buffer are reversed from "0" to "1" after that operation. When the timer A2 counter counts the value written into the timer A2 and the one-shot pulse output of timer A2 is completed, the contents of output polarity set toggle flip-flop 2 are reversed from "0" to "1". Simultaneously, the one-shot pulse of the 8-bit dead-time timer is out__ put for ensuring time, so that "L" levels of U- and U-phase waveforms do not overlap.
7
6
5
4
3
2
1
0
Address Timer A write register 4516 Timer A0 write bit 0 : Write to timer A0 1 : Write to timer A01 Timer A1 write bit 0 : Write to timer A1 1 : Write to timer A11 Timer A2 write bit 0 : Write to timer A2 1 : Write to timer A21
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", this register's contents can be changed from the status after reset (in Fig.76).
Fig. 46 Timer A write flag bit configuration
Timer B2 interrupt request signal Signal output each time Timer B2 becomes 000016 One-shot pulse output with timer A2 Timer A2 Timer A21 Contents of output polarity set toggle flip-flop 2 Reversed pulse output signal with dead-time timer U-phase waveform output U-phase waveform output n1 n1 n2 n2 n3 n4 n3 n4 n5 n6 n5 n6 n7 n8
Fig. 47 U-phase waveform output example in three-phase mode 1 (triangular wave modulation)
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The U-phase waveform output keeps "H" level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from "0" to "1" owing to the timer A2's one-shot pulse output. When the one-shot pulse output of the dead-time timer is completed, "1" of output polarity set toggle flip-flop 2 which has been reversed becomes valid and the U-phase waveform changes to "L" level. Then, when the counter of timer B2 becomes 000016, the timer A2 counter counts the value written into timer A2 and timer A2 starts one-shot pulse output. Simultaneously, the contents of three-phase output polarity set buffer are set into the output polarity set toggle flip-flop 2. However, the U-phase waveform remains "L" level, because the value is the same ("1"). The contents of three-phase output polarity set buffer are reversed from "1" to "0" after that operation. When the one-shot pulse output of timer A2 is completed, the contents of output polarity set toggle flip-flop 2 is reversed from "1" to "0". Simultaneously, the one-shot pulse output of the dead-time timer starts. When the contents of output polarity set toggle flip-flop 2 is reversed from "1" to "0", the U-phase waveform changes its output level from "L" to "H" without waiting for completion of the one-shot pulse output of the dead-time timer. U-phase waveform is generated by repeating the operation above. _ The way to generate U-phase waveform, which is the negative phase of U-phase, is the same as that for U-phase waveform except that the contents of output polarity set toggle flip-flop 2 is treated as the reversed signal from the case of U-phase waveform. _ In this way, U-phase waveform and U-phase waveform, having the negative phase of U-phase, are output from the pins so that their "L" levels do not overlap each other. The width of "L" level can be also modified by changing the value of timer B2, timer A2 or timer A21. _ __ V-, W-phase waveform and V-, W-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation.
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse output port mode
Figure 48 shows the pulse output port mode block diagram. This mode has an 8-bit pulse output port. The waveform output select bits (bits 0 to 2) of waveform output mode register (address 1A16, Figure 49) select use of pulse output port. The 8-bit pulse output port is divided into 4 bits and 4 bits, or 6 bits and 2 bits with the pulse output mode select bit (bit 4) of pulse output data register 1 (address 1C16, Figure 51) ; each of them can be individually controlled.
Set timers A1 and A0 to the timer mode because they are used in the pulse output mode. Additionally, set bit 2 of the corresponding timer Ai mode register to "1" to use a pulse output port because the pulse output port are multiplexed with the TAiOUT (i = 0 to 4). Figure 50 shows the bit configuration of timer A1 and A0 mode registers in the pulse output port mode. Timers A1 and A0 start count when setting the corresponding timer count start flag to "1", and they stop it when clearing that flag to "0".
Pulse width modulation select bit 1 Pulse width modulation output of timer A4 Pulse width modulation output of timer A3 Pulse width modulation output of timer A2
Pulse width modulation select bit 0
Timer A1 Pulse width modulation data bit D15 D14 D13 Pulse output data register 1 D3 D2 Data bus (even) D1 Data bus (odd) D0 Pulse output mode select bit T DQ DQ DQ DQ RTP13 RTP12 RTP11 RTP10 T DQ DQ DQ Reset Waveform output control bit 0 DQ R
D11 D10 D9 D8 Pulse output data register 0 Timer A0
T DQ DQ DQ DQ T Waveform output control bit 0 DQ Polarity select bit R Reset
RTP03 RTP02 RTP01 RTP00
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", the following registers' contents can be changed from the status after reset (in Fig.76) : Waveform output mode register (address 1A16) and Pulse output data registers 0 and 1 (addresses 1C16, 1D16).
Fig. 48 Pulse output port mode block diagram
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Address Waveform output mode register 1A16 Waveform output select bits 000 : Parallel port 001 : RTP1 selected (Valid in pulse mode 0) 010 : RTP0 selected (Valid in pulse mode 0) 011 : In pulse mode 0 RTP1 and RTP0 selected In pulse mode 1 RTP1, RTP03, RTP02, RTP01, RTP00 selected Polarity select bit (Valid for RTP0 in pulse mode 0) 0 : Positive polarity 1 : Negative polarity Pulse width modulation select bit 0 (Valid for RTP1 in pulse mode 0; Valid for RTP1, RTP03, RTP02 in pulse mode 1) 0 : No modulation by timer A2 1 : Modulation by timer A2 Pulse width modulation select bit 1* (Valid in pulse mode 1) 0 : Modulation by timer A2 1 : Modulation for RTP03, RTP02 by timer A2 Modulation for RTP11, RTP10 by timer A3 Modulation for RTP13, RTP12 by timer A4 * when selecting pulse mode 0, fix this bit to "0". Waveform output control bit 0 0 : In pulse mode 0 Disable RTP0 waveform output In pulse mode 1 Disable RTP0 1, RTP00 waveform output 1 : In pulse mode 0 Enable RTP0 waveform output In pulse mode 1 Enable RTP01, RTP00 waveform output Waveform output control bit 1 0 : In pulse mode 0 Disable RTP1 waveform output In pulse mode 1 Disable RTP1, RTP03, RTP02 waveform output 1 : In pulse mode 0 Enable RTP1 waveform output In pulse mode 1 Enable RTP1, RTP0 3, RTP02 waveform output
Pulse mode 0
This mode divides a pulse output port into 4 bits and 4 bits and individually controls them. When setting the pulse output mode select bit to "0", and setting bits 2 and 1 to "0" and bit 0 to "1" of the waveform output select bits, four of RTP13, RTP12, RTP11, and RTP10 become the pulse output ports with RTP1 selected. When setting the pulse output mode select bit to "0", and setting bits 2 and 0 to "0" and bit 1 to "1" of the waveform output select bits, four of RTP03, RTP02, RTP01, RTP00 become the pulse output ports with RTP0 selected. When setting the pulse output mode select bit to "0", and setting bit 2 to "0" and bits 1 and 0 to "1" of the waveform output select bits, the following two groups become the pulse output ports with RTP1 and RTP0 selected: *Four of RTP13, RTP12, RTP11, RTP10 *Four of RTP03, RTP02, RTP01, RTP00. Each time the contents of timer A1 counter become 000016, the contents of pulse output data register 1 (low-order 4 bits at address 1C16) corresponding to RTP13, RTP12, RTP11, RTP10 are output from ports. Each time the contents of timer A0 counter become 000016, the contents of pulse output data register 0 (low-order 4 bits at address 1D16) corresponding to RTP03, RTP02, RTP01, RTP00 are output from ports. When writing "0" to the specified bit of pulse output data register, "L" level is output from the pulse output port when the contents of corresponding timer counter become 000016; when writing "1" to it, "H" level is output from the pulse output port.
7
6
5 0
4 0
3 x
2 1
1 0
0 0
Timer A0 mode register Timer A1 mode register
Address 5616 5716
100 : Fix to "100" in pulse output port mode
x : Not used in pulse output port mode
00 : Fix to "00" in pulse output port mode Clock source select bit 00 : Pf2 selected 01 : Pf16 selected 10 : Pf64 selected 11 : Pf512 selected
Fig. 50 Bit configuration of timer A1 and A0 mode registers in pulse output port mode
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", this register's contents can be changed from the status after reset (in Fig.76).
Fig. 49 Bit configuration of waveform output mode register in pulse output port mode
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ge. ion. icat to chan ecif l sp ubject a a fin es not mits ar li is is : Th metric ice Not e para Som
MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Additionally, pulse width modulation can be applied for the pulse output port RTP1. Because the timer A2 is used for pulse width modulation, actuate timer A2 in the pulse width modulation mode. When any bit of pulse output data is "1", the pulse to which pulse width modulation is applied is output from the pulse output port when the contents of timer A1 counter become 000016. Pulse width modulation by timer A2 is applied when setting the pulse width modulation select bit 0 (bit 4) of waveform output mode register to "1", pulse width modulation select bit 1 (bit 5) to "0," and the pulse width modulation data bit of RTP1 (bit 5) of pulse output data register 0 to "1". RTP03, RTP02, RTP01 and RTP00 can output the contents of pulse output data register 0 by setting the polarity select bit (bit 3) of waveform output mode register. When the polarity select bit is "1", the reversed contents of pulse output data register 0 is output; when that bit is "0", the contents of pulse output data register 0 are output as it is. Figure 52 shows example waveforms in the pulse mode 0. In ports selecting the pulse mode 0, output of RTP03, RTP02, RTP01 and RTP00 is controlled by the waveform output control bit 0 (bit 6) of waveform output mode register; output of RTP13, RTP12, RTP11 and RTP10 is done by the waveform output control bit 1 (bit 7). When setting the waveform output control bit to "1", waveform is output from the corresponding port. When clearing that bit to "0", waveform output from the corresponding port stops, and the port becomes floating. The waveform output control bits are cleared to "0" by reset other than clearing with instructions.
The polarity select bit (bit 3) of waveform output mode register must be "0" to select the positive polarity. The other operations are the same as that of pulse mode 0. Figure 53 shows example waveforms in the pulse mode 1. In ports selecting the pulse mode 1, output of RTP01 and RTP00 is controlled by the waveform output control bit 0 (bit 6) of waveform output mode register; output of RTP13, RTP12, RTP11, RTP10, RTP03 and RTP02 is done by the waveform output control bit 1 (bit 7). When setting the waveform output control bit to "1", waveform is output from the corresponding port. When clearing that bit to "0", waveform output from the corresponding port stops and the port becomes floating. The waveform output control bits are cleared to "0" by reset other than clearing with instructions.
7 x
6 x
5 x
4
3
2
1
0
Address Pulse output data register 1 1C16 RTP10 pulse output data bit RTP11 pulse output data bit RTP12 pulse output data bit RTP13 pulse output data bit Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1
: Not used in pulse output port mode
Pulse mode 1
This mode divides a pulse output port into 6 bits and 2 bits, and individually controls them. When setting the pulse output mode select bit to "1", and setting bit 2 to "0" and bits 1 and 0 to "1" of the waveform output select bits, the following two groups become the pulse output ports: *Six of RTP13, RTP12, RTP11, RTP10, RTP03, RTP02 *Two of RTP01, RTP00. Timer A1 controls six of RTP13, RTP12, RTP11, RTP10, RTP03, and RTP02; timer A0 controls two of RTP01, RTP00. Additionally, pulse width modulation can be applied for the pulse output ports (RTP1, RTP03, RTP02). The pulse width modulation select bit 1 (bit 5) of waveform output mode register selects the type of modulation: the common modulation to six of RTP13, RTP12, RTP11, RTP10, RTP03 and RTP02 or the modulation to every two ports of RTP13 and RTP12, RTP11 and RTP10, RTP03 and RTP02. When setting that bit to "0", the common modulation to six ports is applied; when setting that bit to "1", the modulation to every two ports is applied. The timer A2 is used for the common modulation to six ports; the timers A2, A3 and A4 are used for the modulation to every two ports. Accordingly, actuate the respective timers in the pulse width modulation mode. When any bit of pulse output data is "1", the pulse to which pulse width modulation is applied is output from the pulse output port when the contents of timer A1 counter become 000016. Pulse width modulation by corresponding timers is applied when setting the pulse width modulation select bit 0 of waveform output mode register to "1" and the corresponding pulse width modulation data bits (bits 7 to 5) of pulse output data register 0 to "1".
7
6
5
4
3
2
1
0
Address Pulse output data register 0 1D16 RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit RTP03 pulse output data bit In pulse mode 0 Pulse width modulation data bit of RTP1 In pulse mode 1 Pulse width modulation data bit of RTP03, RTP02 In pulse mode 1 Pulse width modulation data bit of RTP11, RTP10 In pulse mode 1 Pulse width modulation data bit of RTP13, RTP12
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15) is set to "1", this register's contents can be changed from the status after reset (in Fig.76).
Fig. 51 Bit configuration of pulse output data registers 1 and 0 in pulse output port mode
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e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som
IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pulse outpu port (RTP1) example Signal output each time timer A1 becomes 000016 RTP13 RTP12 RTP11 RTP10
Example of pulse width modulation for above pulse output port using timer A2 Signal output each time timer A1 becomes 000016 RTP13 RTP12 RTP11 RTP10
Pulse outpu port (RTP0) example in the case of polarity select bit = "1" Signal output each time timer A0 becomes 000016 RTP03 RTP02 RTP01 RTP00
Fig. 52 Example waveforms in pulse mode 0
Pulse outpu port (6 bits) example Signal output each time timer A1 becomes 000016 RTP13 RTP12 RTP11 RTP10 RTP03 RTP02
Example of pulse width modulation for above pulse output port using timer A2 Signal output each time timer A1 becomes 000016 RTP13 RTP12 RTP11 RTP10 RTP03 RTP02
Fig. 53 Example waveforms in pulse mode 1
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MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
Two independent serial I/O ports are provided. Figure 54 shows a block diagram of the serial I/O ports. Bits 0, 1, and 2 of the UARTi(i = 0,1) Transmit/Receive mode register shown in Figure 55 are used to determine whether to use port P8 as parallel port, clock synchronous serial I/O port, or asynchronous
(UART) serial I/O port using start and stop bits. Figures 56 and 57 show the connections of receiver/transmitter according to the mode. Figure 58 shows the bit configuration of the UARTi Transmit/Receive control register. Each communication method is described below.
Data bus(odd)
Data bus(even) Bit converter 0 0 0 0 0 0 0 D8 RXDi UART receive
1/16 Divider
D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register UART0(3716,3616) UART1(3F16,3E16) Receive register
Bit rate generator
Clock synchronous
Receive control circuit
Receive clock
UART transmission Clock source selection UART0(3116) 1/16 Divider Transmission Transmission clock UART1(3916) Pf2 control circuit Clock synchronous Internal Pf16 Clock synchronous TXDi 1/(n + 1) (Internal clock) Pf64 Transmit register 1/2 Divider Divider Pf512 External Clock synchronous Clock synchronous CLKi (Internal clock) (External clock) Transmit D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register CTSi/RTSi UART0(3316,3216) UART1(3B16,3A16) Data bus (odd) Bit converter
Data bus(even)
Fig. 54 Serial I/O port block diagram
Addresses 3016 3816
76543210
UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register Serial I/O mode select bit 0 0 0 : Parallel port 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal/External clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit 0 : 1 stop bit 1 : 2 stop bits Even/Odd parity select bit 0 : Odd parity 1 : Even parity Parity enable select bit 0 : No parity 1 : With parity Sleep select bit 0 : No sleep 1 : Sleep
Fig. 55 UARTi Transmit/Receive mode register bit configuration
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e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data bus(odd) Data bus(even) Bit Converter Receive buffer register 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0
2 stop bit RXDi Stop bit Stop bit 1 stop bit
Parity Parity bit No parity
7bit 8bit 9bit
9 bit
8bit 9bit Synchronous
7bit 8bit Synchronous
7 bit
Receive register
Synchronous
Fig. 56 Receiver block diagram
Data bus(odd) Data bus(even) Bit Converter Transmit buffer register D8
7bit 9bit Synchronous
D7
D6
D5
D4
D3
D2
D1
D0
2 stop bit "0" Stop bit Stop bit
Parity Parity bit No parity
7bit 8bit 9bit
8bit 9bit Synchronous TXDi
8 bit Synchronous
7 bit
1 stop bit "0"
Transmit register
Fig. 57 Transmitter block diagram
7
MSB/ LSB
6
5
4
3
2
1
0
TX R/C TCS1 TCS0 EPTY
Addresses UART 0 Transmit/Receive control register 0 3416 UART 1 Transmit/Receive control register 0 3C16
BRG count source select bit 0 0 : Select Pf2 0 1 : Select Pf16 1 0 : Select Pf64 1 1 : Select Pf512 CTS, RTS select bit 0 : Select CTS 1 : Select RTS Transmit register empty bit CTS, RTS enable bit 0 : Enable CTS, RTS 1 : Disable CTS, RTS (Input/Output port) Transfer format select bit (Note) 0 : LSB first 1 : MSB first
7 6 5 4 3
RI
Note : This bit is valid in clock synchronous mode. Fix this bit to "0" in UART mode.
2
RE
1
TI
0
TE
SUM PER FER OER
Addresses UART 0 Transmit/Receive control register 1 3516 UART 1 Transmit/Receive control register 1 3D16
Transmit enable flag Transmit buffer empty flag Receive enable flag Receive complete flag Overrun error flag Framing error flag Parity error flag Error sum flag
Fig. 58 UARTi Transmit/Receive control register bit configuration
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK SYNCHRONOUS SERIAL COMMUNICATION
A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 59 will be described. (The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.) Bit 0 of the UARTj Transmit/Receive mode register and UARTk Transmit/Receive mode register must be set to "1" and bits 1 and 2 must be "0". The length of the transmission data is fixed at 8 bits. Bit 3 of the UARTj Transmit/Receive mode register of the clock sending side is cleared to "0" to select the internal clock. Bit 3 of the UARTk Transmit/Receive mode register of the clock receiving side is set to "1" to select the external clock. Bits 4, 5 and 6 are ignored in clock synchronous mode. Bit 7 must always be "0". The clock source is selected by bit 0 (TCS0) and bit 1 (TCS1) of the clock-sending-side UARTj Transmit/Receive control register 0. As shown in Figure 54, the selected clock is divided by (n+1), then by 2, is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is Pfi, Bit Rate = Pfi/ {(n+1)x2} On the clock receiving side, the TCS0 and TCS1 bits of the UARTk Transmit/Receive control register 0 are ignored because an external clock is selected. Bit 2 of the clock-sending-side UARTj Transmit/Receive control reg____ ister 0 is cleared to "0" to select CTSj input. Bit 2 of the clock receiv____ ing side is set to "1" to select RTSk output. Bit 4 of the UART Transmit/Receive control register 0 is used to de____ ____ termine____ whether to use CTS or RTS signal. Bit 4 ____ be "0" when must ____ ____ CTS or RTS signal is used. Bit 4 must be "1" when CTS and RTS sig____ ____ ____ nals are not used. When CTS and RTS signals are not used, CTS/ ____ ____ ____ RTS pin can be used as a normal port. The case using CTS and RTS ____ ____ signals are explained below. However, when CTS and RTS signals ____ are not used, there are no condition of CTSj input, and there is no _____ RTSk output.
TxDj UARTj transmit register
TxDk UARTk transmit register
UARTj transmit buffer register
UARTk transmit buffer register
UARTj receive buffer register RxDj UARTj receive register RxDk
UARTk receive buffer register
UARTk receive register
UARTj Transmit/Receive mode register 0 x x x 0 0 0 1 CLKj UARTj Transmit/Receive control register 0 TX EPTY 0 TCS1 TCS0 CTSj UARTj Transmit/Receive control register 1 SUM PER FER OER RI RE TI TE RTSk CLKk 0
UARTk Transmit/Receive mode register x x x 1 0 0 1
MSB/ LSB
MSB/ LSB
UARTk Transmit/Receive control register 0 TX x EPTY 1 UARTk Transmit/Receive control register 1
x
SUM PER FER OER
RI
RE
TI
TE
Fig. 59 Clock synchronous serial communication
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
Transmission is started when bit 0 (TEj flag) of UARTj Transmit/Re____ ceive control register 1 is "1", bit 1 (TIj flag) of one is "0", and CTSj input is "L". As shown in Figure 60, data is output from TXDj pin each time when transmission clock CLKj changes from "H" to "L". The data is output from the least significant bit. The TIj flag indicates whether the transmit buffer register is empty or not. It is cleared to "0" when data is written in the transmit buffer register and set to "1" when the contents of the transmit buffer register is transferred to the transmit register. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. If bit 2 of UARTj Transmit/Receive control reg____ ister 0 is "1", CTSj input is ignored, and transmission start is controlled only by the TEj flag and TIj flag. Once transmission has ____ started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission is not interrupt ____ when CTSj input is changed to "H" during transmission. The transmission start condition indicated by TEj flag, TIj flag, and ____ CTSj is checked while the TENDj signal (shown in Figure 60) is "H". Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIj flag is cleared to "0" before theTENDj signal goes "H". Bit 3 (TXEPTYj flag) of UARTj Transmit/Receive control register 0
changes to "1" at the next cycle just after the TENDj signal goes "H" and changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission has completed. When the TIj flag changes from "0" to "1", the interrupt request bit in the UARTj transmit interrupt control register is set to "1". In only UART0, data can be output to a maximum of 3 external receive devices. This is realized under the condition in which the internal clock is selected and the transmission clock is output from one of pins CLK0, CLKS0 (multiplexed with RXD0) and CLKS1 (multiplexed ____ ____ with CTS0/RTS0). Make sure that do not switch the selection of the clock during transmission. Figure 61 shows an external connection example. Plural output of transmit clock mode is set with bits 1 and 0 of the particular function select register 1. Additionally, it is necessary to se___ ___ lect the internal clock, disable CTS and RTS, receive and D-A output with the UART0 Transmit/Receive mode register, UART0 Transmit/ Receive control registers 0 and 1, and A-D control register 1. Figure 62 shows the other registers bit configuration in plural output of transmit clock mode and Figure 63 shows the particular function select register 1 bit configuration . Table 6 shows the function of the particular function select register 1's bits 1 and 0, which is the output pin of transmit clock select bits: TC1 and TC0. According to this table, select the CLK0, CLKS0 or CLKS1 pin corresponding to the contents of TC1 and TC0, and output the transmit clock.
1/Pfi x (n + 1) x 2 Transmission clock TEj TIj Write in transmit buffer register CTSj 1/Pfi x (n + 1) x 2 CLKj TENDj TXDj TXEPTYj D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Stopped because TEj = "0" Transmit register Transmit buffer register
Fig. 60 Clock synchronous serial I/O timing
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
TXD0 CLKS1 UART0 CLKS0 CLK0
DIN CLK
DIN CLK
DIN CLK
Note: This is available in clock synchronous serial I/O, using internal clock and transmission mode.
Fig. 61 External connection example in plural output of transmit clock mode
7 0
6
5
4
3 0
2 0
1 0
0 1
UART0 Transmit/Receive mode register 0 0 1 : Clock synchronous 0 : Internal clock This bit must be "0"
Address 3016
7
6
5
4 1
3
2
1
0 UART0 Transmit/Receive control register 0 1 : Disable CTS, RTS
Address 3416
7
6
5
4
3
2 0
1
0 UART0 Transmit/Receive control register 1 0 : Disable receive Address 1F16
Address 3516
7 0
6
5
4
3
2
1
0 A-D control register 1 0
: Disable D-A output
Receive starts when bit 2 (REk flag) of UARTk Transmit/Receive control register 1 is set to "1". ____ The RTSk output is "H" when the REk flag is "0" and goes "L" when the REk flag changed to "1" and the TIk flag did to "0". It goes back to "H" when receive starts. The TIk flag is cleared to "0" by write dummy ____ data to the transmit buffer register. It is ready to receive when RTSk output is "L". The data from the RxDk pin is retrieved and the contents of the receive register is shifted by 1 bit each time when the transmission clock CLKj changes from "L" to "H." When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (RIk flag) of UARTk Transmit/Receive control register 1 is set to "1". In other words, the setting "1" to the RIk flag indicates that the receive buffer register contains the received data. When the RIk flag changes from "0" to "1", the interrupt request bit in the UARTk receive interrupt control register is set to "1". Bit 4 (OERk flag) of UARTk Transmit/Receive control register 1 is set to "1" when the next data is transferred from the receive register to the receive buffer register while RIk flag is "1", and indicates that the next data was transferred to the receive register before the contents of the receive buffer register was read. RIk flag is automatically cleared to "0" when the low-order byte of the receive buffer register is read or when the REk flag is cleared to "0". The OERk flag is cleared when the REk flag is cleared or port P8 is set to a parallel port. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode. When reading the contents of the receive buffer register, the received data is pulled from the least significant bit (LSB) in the received order if bit 7 (TEM) of the UARTj Transmit/Receive control registers 0 is "0". If bit 7 (TEM) is "1", the received data is pulled from the most significant bit (MSB). As shown in Figure 54, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no need to sent data from UARTk to UARTj.
Fig. 62 Other registers except special function select register 1 bit configuration in plural output of transmit clock mode Table 6. Output pin of transmit clock select bits and pins' function Output pin of transPin name mit clock select bits ____ ____ TC1 TC0 P81/CLK0 P82/RXD0 P80/CTS0/RTS0/DA0 ____ ____ 0 0 CLK0 RXD0 P80/CTS0/RTS0/DA0 0 1 CLK0 "H" (Note) P80 1 0 "H" CLKS2 P80 1 1 "H" "H" (Note) CLKS1
Note: It outputs "H" when bit 2 of the port P8 direction register is "1", and it becomes floating when bit 2 is "0".
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 Particular function select register 1 (6D16) Transmit clock output pin select bit 00 : Normal mode (output only to CLK0) 01 : Plural clocks specified; output to CLK0 10 : Plural clocks specified; output to CLKS0 11 : Plural clocks specified; output to CLKS1 Internal clock stop select bit at WIT (Note 1) 0 : Clock for peripheral function and watchdog timer are operating at WIT 1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT Watchdog timer's select bit (Note 1) 0 : Exclusive clock deviding circuit output (Wf512, Wf32) is used as clock for watchdog timer. Clock (Wf512, Wf32) for watchdog timer does not change in hold. 1 : Clock for peripheral device deviding circuit output (Pf512, Pf32) is used as clock for watchdog timer. Clock (Pf512, Pf32) for watchdog timer changes in hold. Watchdog timer exclusive clock dividing circuit is stopped. Signal output stop select bit (Note 1) Refer to Table 8. Expansion function select bit (Note 2) Refer to Figure 62. Pull-up select bit 0 (Note 3) 0 : With no pull-up for P57, P56, P55, P54 1 : With pull-up for P57, P56, P55, P54 Pull-up select bit 1 (Note 3) 0 : With no pull-up for P95 1 : With pull-up for P95
TC1 TC0
Control bits affected by expansion function select bit Register Address Bit A-D control register 1 1F16 5 Chip select area register 6316 2, 5, 6, 7 Particular function select register 0 6C16 0, 1, 5, 6 Particular function select register 1 6D16 2, 3, 4
Control registers affected by expansion function select register Register Address Waveform output mode register 1A16 Dead-time timer 1B16 Pulse output data register 1 1C16 Pulse output data register 0 1D16 Timer A write flag 4516 ____ INT4 interrupt control register 6E16
Notes 1: Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to "1." 2: After bit 5 is set to "1" once, bit 5 cannot be cleared to "0" except external reset and software reset. 3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0-7.
Fig. 63 Particular function select register 1 bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selection of transfer format
In clock synchronous serial communication, transfer format can be selected by bit 7 of the Transmit/Receive control register 0. When bit 7 is "0", transfer format is LSB first. When bit 7 is "1", transfer format is MSB first. This function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter's operation is the same in both transfer formats. Figure 64 shows the connection relation.
Bit 7 in Transmit/Receive control register 0
Write to transmit buffer register Transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 Transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0
Read from receive buffer register Receive buffer register D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register D7 D6 D5 D4 D3 D2 D1 D0
Data bus DB7 DB6 0 (LSB first) DB5 DB4 DB3 DB2 DB1 DB0
Data bus DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data bus DB7 DB6 1 (MSB first) DB5 DB4 DB3 DB2 DB1 DB0
Data bus DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Fig. 64 Connection relation between transmit buffer register, receive buffer register, and data bus
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I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS SERIAL COMMUNICATION
Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, bit 0 of UARTi Transmit/ Receive mode register is "1", bit 1 is "0", and bit 2 is "1". Bit 3 is used to select an internal clock or an external clock. If bit 3 is "0", an internal clock is selected and if bit 3 is "1", then external clock is selected. If an internal clock is selected, bit 0 (TCS0) and bit 1 (TCS1) of UARTi Transmit/Receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal I/O pin. The selected internal or external clock is divided by (n+1), then by 16, and is passed through a control circuit to create the UART transmission clock or UART receive clock. Therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. If the selected clock is an internal clock Pfi or an external clock fEXT, Bit Rate = (Pfi or fEXT) / {(n+1)x16} Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
Bit 5 is a select bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. Bit 6 is the parity bit select bit which indicates whether to add parity bit or not. Bits 4 to 6 must be set or reset according to the data format used in the communicating devices. Bit 7 is the sleep select bit. The sleep mode is described later. The UARTi Transmit/Receive control register 0 bit 2 is used to deter____ ____ mine whether to use CTSi input or RTSi output. ____ ____ CTSi input is used if bit 2 is "0" and RTSi output is used if bit 2 is "1". ____ If CTSi input is selected, the user can control whether to stop or start ____ transmission by external CTSi input. Bit 4 of the UART Transmit/Receive control register 0 is used to de___ ___ termine____ whether to use CTS or RTS signal. Bit 4 must be "0" when ____ ___ ___ CTS or RTS signal is used. Bit ___ 4 must be "1" when CTS or RTS sig___ ___ ___ nal is not used. When CTS or RTS signal is not used, CTS/RTS pin ___ ___ can be used as a normal port. The case using CTS and RTS signals ___ ___ are explained below. However,____ CTS and RTS signals are not when ____ used, there are no condition of CTSi input, and there is no RTSi output. Clear UARTj Transmit/Receive control register 0 bit 7 to "1" in asynchronous communication.
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____
Transmission
Transmission is started when bit 0 (TEi flag) of UARTi ____ Transmit/Receive____ register 1 is "1", bit 1 (TIi flag) is "0", and CTSi input is control "L" if CTSi input is selected. As shown in Figures 65 and 66, data is output from the TXDi pin with the stop bit or parity bit specified by bits 4 to 6 of UARTi Transmit/Receive mode register. The data is output from the least significant bit. The TIi flag indicates whether the transmit buffer is empty or not. It is cleared to "0" when data is written in the transmit buffer, and is set to "1" when the contents of the transmit buffer register is transferred to the transmit register. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condition is satisfied.
Once transmission has started, the TEi flag, TIi flag, and CTSi signal ____ (if CTSi input is selected ) are ignored until data transmission is completed. Therefore, transmission does not stop until it completes event if the TEi flag is cleared during transmission. The transmission start condition indicated by TEi flag, TIi flag, and ____ CTSi is checked while the TENDi signal shown in Figure 65 is "H". Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIi flag is cleared to "0" before the TENDi signal goes "H". Bit 3 (TXEPTYi flag) of UARTi Transmit/Receive control register 0 changes to "1" at the next cycle just after the TENDi signal goes "H" and changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from "0" to "1", the interrupt request bit of the UARTi transmit interrupt control register is set to "1".
(1/Pfi or 1/fEXT) x (n + 1) x 16 Transmission clock
TEi
TIi Written in transmit buffer register CTSi Transmit register Transmit buffer register
TENDi Start bit TXDi Parity bit Stop bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Stopped because TEi = "0" ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
TXEPTYi
Fig. 65 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
(1/Pfi or 1/fEXT) x (n + 1) x 16 Transmission clock
TEi
TIi Written in transmit buffer register TENDi Start bit TXDi Stop bit Transmit register Transmit buffer register Stop bit Stopped because TEi = "0" ST D0 D1 D2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
TXEPTYi
Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
Receive is enabled when bit 2 (REi flag) of UARTi Transmit/Receive control register 1 is set to "1." As shown in Figure 67, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. ____ If RTSi output is selected by ____ bit 2 of UARTi Transmit/Receive setting control register 0 to "1", the RTSi output is ____ "H" when the REi flag is "0". When the REi flag changes to "1", the RTSi output goes "L" to indicate receive ready and returns to "H" once receive has started. In ____ other words, RTSi output can be used to determine externally whether the receive register is ready to receive. The entire transmission data bits are received when the start bit passes the final bit of the receive block shown in Figure 56. At this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (Rli flag) of UARTi Transmit/Receive control register 1 is set to "1." In other words, the RIi flag indicates that the ____ receive buffer register contains data when it is set to "1." If RTSi out____ put is selected, RTSi output goes "L" to indicate that the register is ready to receive the next data. The interrupt request bit of the UARTi receive interrupt control register is set to "1" when the RIi flag changes from "0" to "1". Bit 4 (OERi flag) of UARTi Transmit/Receive control register 1 is set to "1" when the next data is transferred from the receive register to the receive buffer register while the RIi flag is "1", in other words, when an overrun error occurs. If the OERi flag is "1", it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. Bit 5 (FERi flag) is set to "1" when the number of stop bits is less than required (framing error). Bit 6 (PERi flag) is set to "1" when a parity error occurs. Bit 7 (SUMi flag) is set to "1" when either the OERi flag, FERi flag, or the PERi flag is set to "1." Therefore, the SUMi flag can be used to determine whether there is an error. The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is performed while transferring the contents of the receive register to the receive buffer register. The Rli, FERi, and PERi flags are cleared
to "0" when reading the low-order byte of the receive buffer register or when writing "0" to the REi flag or when setting to a parallel port. The OERi and SUMi flags are cleared to "0" when writing "0" to the REi flag or when setting to a parallel port. The SUMi flag is cleared to "0" when the OERi, FERi, PERi flags are cleared to "0" all.
Sleep mode
The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial I/O. The microcomputer enters the sleep mode when bit 7 of UARTi Transmit/Receive mode register is set to "1." The operation of the sleep mode for an 8-bit asynchronous communication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asynchronous communication) of the received data is "0". Also the RIi, OERi, FERi, PERi, and the SUMi flag are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is "1". The following is an example of how the sleep mode can be used. The main microcomputer first sends data: bit 7 is "1" and bits 0 to 6 are set to the address of the subordinate microcomputer to be communicated with. Then all subordinate microcomputers receive this data. Each subordinate microcomputer checks the received data, clears the sleep bit to "0" if bits 0 to 6 are its own address and sets the sleep bit to "1" if not. Next, the main microcomputer sends data with bit 7 cleared. Then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to "1" will not. In this way, the main microcomputer is able to communicate only with the designated microcomputer.
Pfi or fEXT
REi Stop bit RXDi Start bit Check to be "L" level Receive Clock RIi Starting at the falling edge of start bit D0 Data fetched D1 D7 Start bit
RTSi
Fig. 67 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter. The use of A-D converter or the use of comparator can be selected for each A-D input pin. The contents of the comparator function select register specify it. Figure 68 shows a block diagram of the A-D converter.
VREF connection select bit VREF AVSS Ladder network Vref Comparator function select register (0: A-D converter, 1: Comparator) (Address 6416) A-D control register 0 (Address 1E16) A-D control register 1 (Address 1F16)
Selector 1
Control circuit
Selector
Successive approximation register
Comparator result register (Address 6616)
Address A-D register 0 (2116) A-D register 1 (2316) A-D register 2 (2516) A-D register 3 (2716) A-D register 4 (2916) A-D register 5 (2B16) A-D register 6 (2D16) A-D register 7 (2F16)
Address A-D register 0 (2016) A-D register 1 (2216) A-D register 2 (2416) A-D register 3 (2616) A-D register 4 (2816) A-D register 5 (2A16) A-D register 6 (2C16) A-D register 7 (2E16) Decoder Comparator
Data bus (odd) Data bus (even) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7/ADTRG Selector A-D conversion speed selection 0 f(XIN) 1/2 1 0 1/2 Pf2 1/2 1 Pf2 Pf4 Pf8 Frequency select flag 0, 1 AD
1 Clock source select bit (bit 6 of processor mode register 1)
1 Clock source for peripheral 1/2 devices select bit (bit 2 of processor mode register 1)
Fig. 68 A-D converter block diagram
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 69 shows the comparator function select register (address 6416) bit configuration. Bits 7 to 0 correspond to channels 7 to 0 respectively. Each channel can be selected as either an A-D converter or a comparator. When the bit is "0", the channel corresponding to it functions as a 10-bit or an 8-bit A-D converter. When the bit is "1", the channel functions as a comparator. When selecting an A-D converter, an input voltage to a selected analog input pin is A-D converted and the result is stored into the A-D register. When selecting a comparator, D-A conversion is performed to the value of which high-order 8 bits are the value stored in an even address of the A-D converter and of which low-order 2 bits are "102." Then, this D-A converted value is compared with the voltage supplied to an analog input pin. After the comparison, when the voltage supplied to an analog input pin is higher, "1" is stored into the comparator result register (address 6616) shown in Figure 70. When it is lower, "0" is stored into that register. Be sure to perform only read to the A-D register of which channel is selected as an A-D converter, and perform only write to the A-D register of which channel is selected as a comparator. Additionally, do not write to the comparator function select register and the A-D register while an A-D converter or a comparator is operating. Port direction register's bits corresponding to pins to be A-D converted must be "0" (input mode) because analog input ports are multiplexed with port P7. Figure 71 shows the bit configuration of the A-D control register 0 (address 1E16) and the A-D control register 1 (address 1F16). An operation clock (AD) of an A-D converter or a comparator can be selected with bit 7 of the A-D control register 0 and bit 4 of the A-D control register 1. When bit 4 (frequency select flag 1) of the A-D control register 1 is "0", AD becomes Pf8 when bit 7 (frequency select flag 0) of the A-D control register 0 is "0", AD becomes Pf4 when bit 7 of the A-D control register 0 is "1". When the frequency select flag 1 is "1", AD becomes Pf2 when the frequency select flag 0 is "0", AD becomes 1 when the frequency select flag 0 is "1". The last case is used when 1 is forcibly used as AD in high-speed running (f(XIN) > 1 > 12.5 MHz). However, this selection is available only in 8-bit resolution mode. AD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. Bit 3 of A-D control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. The conversion result is regarded as 10-bit data when bit 3 is "1" and as 8-bit data when bit 3 is "0". When the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even address of the corresponding A-D register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd address are "0000002" when read. When the conversion result is used as 8-bit data, the high-order 8 bits of the 10-bit A-D conversion result are stored in even address of the corresponding A-D register. In this case, the value at the A-D register's odd address is "0016" when read. Whether to connect the reference voltage input (VREF) with the lad-
der network or not depends on bit 5 of the A-D control register 1. The VREF pin is connected when bit 5 is "0" and is disconnected when bit 5 is "1" (High impedance state). When A-D or D-A conversion is not performed, current from the VREF pin to the ladder network can be cut off by disconnecting ladder network from the VREF pin. Before starting A-D or D-A conversion, wait for 1 s or more after clearing bit 5 to "0".
7
6
5
4
3
2
1
0
Address Comparator function select register 6416 "0" : Select A-D converter "1" : Select comparator AN0 pin comparator function select bit AN1 pin comparator function select bit AN2 pin comparator function select bit AN3 pin comparator function select bit AN4 pin comparator function select bit AN5 pin comparator function select bit AN6 pin comparator function select bit AN7 pin comparator function select bit
Fig. 69 Comparator function select register bit configuration
7
6
5
4
3
2
1
0
Address Comparator result register 6616 "0" : ANi input level is lower than set digital value "1" : ANi input level is higher than set digital value AN0 pin comparator result bit AN1 pin comparator result bit AN2 pin comparator result bit AN3 pin comparator result bit AN4 pin comparator result bit AN5 pin comparator result bit AN6 pin comparator result bit AN7 pin comparator result bit
Note: Do not access with the SEB or CLB instruction.
Fig. 70 Comparator result register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation mode
The operation mode is selected by bits 3 and 4 of A-D control register 0 and bit 2 of A-D control register 1. The available operation modes are one-shot, repeat, single sweep, repeat sweep 0, and repeat sweep 1. Either an A-D converter or a comparator can be selected respectively for every pin in the following 5 modes. The following description applies to the case where the bit of the comparator function select register is "0" and an A-D converter is selected. It also applies to a comparator's operation except that an A-D conversion is changed to a comparator operation and the result of a comparison is stored into the comparator result register.
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register 0 are "0" and bit 2 of A-D control register 1 is "0". The A-D conversion pins are selected with bits 0 to 2 of A-D control register 0. A-D conversion can be started by a software trigger or by an external trigger. A software trigger is selected when bit 5 of A-D control register 0 is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion or comparator operation is started when bit 6 (A-D conversion start flag) is set to "1."
When the bit of comparator function select register is "0" and bit 3 of A-D control register 1 is "1", A-D conversion ends after 59 fAD cycles, and the interrupt request bit of the A-D interrupt control register is set to "1." At the same time, A-D control register 0 bit 6 (A-D conversion start bit) is cleared to "0" and A-D conversion stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin. When the bit of the comparator function select register is "1", a comparator operation ends after 14 fAD cycles and the interrupt request bit of the A-D interrupt control register is set to "1". At the same time, the A-D control register 0 bit 6 (A-D conversion start bit) is cleared to "0" and the comparator operation stops. The result of the comparison is stored into the bit of the comparator result register corresponding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D _____ conversion start bit is "1" and the ADTRG input changes from "H" to "L". In this case, the pins that can be used for A-D conversion are AN0 _____ to AN6 because the ADTRG pin is multiplexed with analog voltage input pin AN7. This operation is the same as that for software trigger except that the A-D conversion start bit is not cleared after A-D conversion and a retrigger can be available during A-D conversion.
Address 7 x 6 x 5 4 3 2 1 0 A-D control register 1 1F16 A-D sweep pin select bit When single sweep or repeat sweep mode 0 is selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 - AN3 (4 pins) 1 0 : AN0 - AN5 (6 pins) 1 1 : AN0 - AN7 (8 pins) When repeat sweep mode 1 is selected (1 pins) 0 0 : AN0 (2 pins) 0 1 : AN0, AN1 1 0 : AN0 - AN2 (3 pins) 1 1 : AN0 - AN3 (4 pins) A-D operation mode select bit 1 0 : Other than repeat sweep mode 1 1 : Repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode A-D converter frequency select bit 1 VREF connection select bit (Note 5) 0 : VREF is connected 1 : VREF is not connected These bits are not used for A-D converter.
Address 7 6 5 4 3 2 1 0 A-D control register 0 1E16 Analog input select bit 0 0 0 : Select AN0 0 0 1 : Select AN1 0 1 0 : Select AN2 0 1 1 : Select AN3 1 0 0 : Select AN4 1 0 1 : Select AN5 1 1 0 : Select AN6 1 1 1 : Select AN7 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 Trigger select bit 0 : Software trigger 1 : ADTRG input trigger A-D conversion start bit 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency select bit 0
Bit 6 at address 5F16 (Note 1)
Bit 2 at address 5F16 (Note 2)
0 0 1
A-D conversion frequency select bit fAD Bit 1 Bit 0 0 0 f(XIN)/16 0 1 f(XIN)/8 1 0 f(XIN)/4 1 1 f(XIN)/2 (Note 3) 0 0 f(XIN)/8 0 1 f(XIN)/4 1 0 f(XIN)/2 1 1
Bit 6 at address 5F16 (Note 1)
Bit 2 at address 5F16 (Note 2)
0 1 1
A-D conversion frequency select bit Bit 1 Bit 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
fAD f(XIN)/8 f(XIN)/4 f(XIN)/2 f(XIN) (Note 4) f(XIN)/4 f(XIN)/2 f(XIN)
Notes1, 2: Refer to Figure 9 Processor mode register 1 bit configuration. 3: When f(XIN) > 25 MHz, this can be selected only in 8-bit resolution mode.
Notes 4: When f(XIN) > 12.5 MHz, this can be selected only in 8-bit resolution mode. 5: When the expansion function select bit (bit 5 of particular function select register 1 ; refer to Fig. 62) is "1", bit 5 can be written and changed.
Fig. 71 A-D control register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
Repeat mode is selected when bit 3 of A-D control register 0 is "1", bit 4 is "0" and bit 2 of A-D control register 1 is "0". The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is generated in this mode. Furthermore, if software trigger is selected, the A-D conversion start bit is not cleared. The contents of the A-D register can be read at any time. Be sure not to write to the A-D register corresponding to the pins selected for a comparator during operation.
(5) Repeat sweep mode 1
Repeat sweep mode 1 is selected when bit 3 of A-D control register 0 is "1", bit 4 is "1" and bit 2 of A-D control register 1 is "1". The difference from the repeat sweep mode 0 is that A-D conversion for one unselected pin is performed each time when A-D conversion for selected pins is completed and A-D conversion is repeated once again from AN0 pin. The number of analog input pins to be swept is also different. The analog input pins for repeatedly sweep are selected with bits 1 and 0 of A-D control register 1. The contents of these pins are used to select one pin, two pins, three pins, or four pins. The unselected pins are converted from the pin next to the pins selected as repeat sweep pins. No interrupt request is generated. Furthermore, if software trigger is selected, the A-D conversion start bit is not cleared. The A-D register can be read at any time. Be sure not to write to the A-D register corresponding to the pins selected for a comparator during operation. Note: Clear the interrupt request bit of the A-D interrupt control register (bit 3 at address 7016) before using the A-D interrupt. It is because the interrupt request bit is undefined just after reset.
(3) Single sweep mode
Single sweep mode is selected when bit 3 of A-D control register 0 is "0", bit 4 is "1" and bit 2 of A-D control register 1 is "0". In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pins are selected by bits 1 and 0 of the A-D control register 1 (address 1F16). Two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with a software trigger or with an external trigger input. A software trigger is selected when bit 5 is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion is started when A-D control register 0 bit 6 (A-D conversion start bit) is set to "1." When A-D conversion of all selected pins end, the interrupt request bit of the A-D conversion interrupt control register is set to "1." At the same time, A-D conversion start bit is cleared to "0" and A-D conversion stops. When an external trigger is selected, A-D conversion starts when _____ the A-D conversion start bit is "1" and the ADTRG input changes from "H" to "L". In this case, the A-D conversion result which is stored in _____ the A-D register 7 becomes invalid because the ADTRG pin is multiplexed with AN7 pin. The operation by external trigger is the same as that by software trigger except that the A-D conversion start bit is not cleared to "0" after A-D conversion and a retrigger can be available during A-D conversion.
(4) Repeat sweep mode 0
Repeat sweep mode 0 is selected when bit 3 of A-D control register 0 is "1", bit 4 is "1" and bit 2 of A-D control register 1 is "0". The difference from the single sweep mode is that A-D conversion does not stop after conversion for all selected pins, but repeats again from the AN0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if software trigger is selected, the A-D convension start bit is not cleared. The A-D register can be read at any time. Be sure not to write to the A-D register corresponding to the pins selected for a comparator during operation.
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The D-A converter is an 8-bit R-2R method D-A converter and consists of two independent D-A converters. Figure 72 shows the block diagram of the D-A converter and Figure 73 shows the bit configuration of A-D control register 1. D-A conversion is performed by writing a value in the corresponding D-A register. The conversion result is output by bits 6 and 7 of A-D control register 1 (address 1F16). When bit 7 is "1", the conversion result is output from DA0 pin. When bit 6 is "1", the conversion result is output from DA1pin. The output analog voltage V is determined according to the value n ("n" is a decimal number) set in the D-A register. V = VREF x n/256 (n = 0 to 255) VREF : Reference voltage The D-A output enable bit is cleared to "0" at reset. Whether to connect the reference voltage input (VREF) with the ladder network or not depends on bit 5 of the A-D control register 1. The VREF pin is connected when bit 5 is "0" and is disconnected when bit 5 is "1" (High impedance state).
When A-D or D-A conversion is not performed, current from the VREF pin to the ladder network can be cut off by disconnecting ladder network from the VREF pin. Before starting A-D or D-A conversion, wait for 1 s or more after clearing bit 5 to "0". An external buffer must be connected when connecting to a low impedance load because there is no built-in D-A output buffer.
76543210 xxxxx
A-D control register 1
Address 1F16
Not used for D-A converter VREF connection select bit (Note) 0 : VREF is connected 1 : VREF is not connected D-A1 output enable bit 0 : Disable output 1 : Enable output D-A0 output enable bit 0 : Disable output 1 : Enable output Note : When the expansion function select bit (bit 5 of peripheral function select register 1 ; refer to Fig. 62) is "1," bit 5 can be written and changed.
Fig. 73 A-D control register 1 bit configuration
Data bus (even) VREF connection select VREF D-A register 0 (Address 6816) D-A register 1 (Address 6A16)
R-2R ladder network AVSS AVSS
R-2R ladder network
D-A0 output enable bit
D-A1 output enable bit
D-A0 pin
D-A1 pin
Fig. 72 D-A converter block diagram
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution sequence caused by software runaway and others. Figure 74 shows the block diagram of the watchdog timer. The watchdog timer consists of a 12-bit binary counter. The watchdog timer counts clock Wf32/Pf32, which is obtained by dividing the peripheral devices' clock Pf2 by 16; or clock Wf512/Pf512, which is obtained by doing it by 256. The watchdog timer frequency select register shown in Figure 75 selects which clock is counted. Wf512/Pf512 is selected when its contents are "0", and Wf32/Pf32 is selected when they are "1". They are cleared to "0" after reset. The watchdog timer clock select bit (bit 3 of particular function select register 1; Figure 62) selects use of clock Wf512/Wf32 or Pf512/Pf32 as the clock source of watchdog timer. When selecting Wf512/Wf32, the clock source of watchdog timer (Wf512/Wf32) is not active during Hold state. When selecting Pf512/Pf32, the clock source of watchdog timer (Pf512/Pf32) is active during Hold state, however, current consumption can be reduced. It is because the Wf512/Wf32 division circuit stops. FFF16 is set in the watchdog timer when "L" or 2Vcc is applied to the ______ RESET pin, STP instruction is executed, data is written to the watchdog timer, or the most significant bit of the watchdog timer becomes "0". After FFF16 is set in the watchdog timer, when the watchdog timer counts the clock source by 2048 counts, the most significant bit of watchdog timer becomes "0", the watchdog timer interrupt request bit is set to "1", and FFF16 is set again in the watchdog timer. Normally, a program is written so that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes "0". If this routine is not executed owing to unexpected program execution and others, the most significant bit of the watchdog timer becomes "0" and an interrupt is generated. The microcomputer can be reset by writing "1" to bit 3 (software reset bit) of processor mode register 0 in the interrupt routine, described in Figure 16 in the interrupt section, and generating a reset pulse. ______ The watchdog timer stops its function when the RESET pin voltage is raised to double the Vcc voltage. The watchdog timer can also be used to return from when the clock is stopped by the STP instruction. Refer to the section on the clock generating circuit for more details. The watchdog timer also becomes Hold state during Hold state and the clock input to it is stopped.
Clock source for peripheral devices Pf2 1/8 Pf16 1/2 1/2 1/8 Hold request Pf512
Pf32
Watchdog timer frequency select register Hold request 1/16 Wf32 1/16 Wf512 Watchdog timer clock select bit Write to watchdog timer Address 6016
Wachdog timer
Set FFF16
RESET
2Vcc detection
STP instruction
S R
Q
Pf16 STP return select bit
Fig. 74 Watchdog timer block diagram
7
6
5
4
3
2
1 0
0
Address Watchdog timer frequency 6116 select register 0 : W f512 or Pf512 selected 1 : W f32 or Pf32 selected This bit must be fixed to "0."
Fig. 75 Watchdog timer frequency select register bit configuration
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
______
INPUT/OUTPUT PINS
Ports P0 to P11 all have the direction register and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is "1", and an input pin when it is "0". When a pin is programmed for output, the data is written to its port latch and it is output to the output pin. When a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. Accordingly, a previously output value can be read correctly even when the output "H" voltage is lowered or the output "L" voltage is raised owing to an external load and others. A pin programmed as an input pin is floating, and the value input to the pin can be read. When a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. Additionally, ports P95, P54 to P57 include pull-up transistors. The pull-up function of ports is selected with bits 7 and 6 of the particular function select register 1. Refer to the section on Interrupts for the pull-up function. Figures 78 and 79 show block diagrams of ports P0 to P11 in the _ single-chip mode and E output. Ports P0 to P4, P10 and P11 are also used as pins of address, data and control signals. Refer to the section on Processor mode for more details.
Reset is released when the RESET pin is returned to "H" level after holding it at "L" level while the supply voltage is at 5V 10%. As the result, program execution starts at the address formed by setting the address A23-A16 to 0016, A15-A8 to the contents of address FFFF16, and A7-A0 to the contents of address FFFE16. Figure 76 shows the status of the internal registers during reset. Figure 77 shows an example of a reset circuit. When a stabilized clock is input from the external to the oscillation circuit, the reset input voltage must be held 0.9V or lower when the supply voltage reaches 4.5V. When connecting a resonator to the oscillation circuit, return the reset input voltage from "L" to "H" after the main-clock oscillation is fully stabilized
Power on
VCC RESET VCC 0V RESET 0V
4.5V
0.9V
Fig. 77 Reset circuit example (perform careful evaluation at system design before using)
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IN LIM E
A
RY
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P9 direction register Port P10 direction register Port P11 direction register Waveform output mode register Pulse output data register 1 Pulse output data register 0 A-D control register 0 A-D control register 1 UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register UART 0 Transmit/Receive control register 0 UART 1 Transmit/Receive control register 0 UART 0 Transmit/Receive control register 1 UART 1 Transmit/Receive control register 1 Count start register One-shot start register Up-down register Timer A write register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 (0416)*** (0516)*** (0816)*** 0 (0916)*** (0C16)*** (0D16)*** (1016)*** (1116)*** (1416)*** (1516)*** (1816)*** (1916)*** (1A16)*** (1C16)*** (1D16)*** 0 0 0 0016 0016 0000 0000 0016 0016 0016 0016 0016 000000 0016 0016 0016 0016 0000 Watchdog timer Watchdog timer frequency select register Chip select control register Chip select area register Comparator function select register Comparator result register D-A register 0 D-A register 1 Particular function select register 0 Particular function select register 1 INT4 interrupt control register INT3 interrupt control register A-D interrupt control register UART 0 transmit interrupt control register UART 0 receive interrupt control register UART 1 transmit interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Processor status register PS Program bank register PG Program counter PCH Program counter PCL Direct page register DPR Data bank register DT
Address (6016)*** (6116)*** FFF16 00
(6216)*** 0 0 0 0 0 0 0 0 (6316)*** 0 0 0 000
(6416)*** 0 0 0 0 0 0 0 0 (6616)*** 0 0 0 0 0 0 0 0 (6816)*** 0 0 0 0 0 0 0 0 (6A16)*** 0 0 0 0 0 0 0 0 (6C16)*** 0 0 0 0 0 0 0 0 (6D16)*** 0 0 0 0 0 0 0 0 (6E16)*** 000000
(6F16)*** 0 0 0 0 0 0 0 0 (7016)*** (7116)*** (7216)*** (7316)*** (7416)*** (7516)*** (7616)*** (7716)*** (7816)*** (7916)*** (7A16)*** (7B16)*** (7C16)*** (7D16)*** (7E16)*** (7F16)*** ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000
(1E16)*** 0 0 0 0 0 ? ? ? (1F16)*** 0 0 0 0 0 0 1 1 (3016)*** (3816)*** (3416)*** 0 (3C16)*** 0 0016 0016 01000 01000
(3516)*** 0 0 0 0 0 0 1 0 (3D16)*** 0 0 0 0 0 0 1 0 (4016)*** (4216)*** 0016 00000
(4416)*** 0 0 0 0 0 0 0 0 (4516)*** (5616)*** (5716)*** (5816)*** (5916)*** (5A16)*** (5B16)*** 0 0 1 (5C16)*** 0 0 1 (5D16)*** 0 0 1 0016 0016 0016 0016 0016 0000 0000 0000 000
000??0001?? 0016 Contents of FFFF16 Contents of FFFE16 000016 0016
(5E16)*** 0 0 0 0 0 0 0 0 (5F16)*** 0016
Contents of other registers and RAM are not initiallzed and must be initiallzed by software.
Note : Bit 0 of chip select control register (address 6216) becomes "0" when CNVss pin level is "L"; that bit becomes "1" when the pin level is "H".
Fig. 76 Microcomputer internal registers status after reset
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MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Port P00 to P07, P10 to P17, P20 to P23, P27, P30 to P33, P43 to P46, P100 to P107, P110 to P117 (Inside dotted-line not included) Port P40, P41, P47, P51, P53, P61 to P67, P86 (Inside dotted-line included)
Direction register
Data bus
Port latch
* Port P70 to P76 (Inside dotted-line not included) * Port P77 (Inside dotted-line included)
Direction register
Data bus
Port latch
Analog input
* Port P42, P83, P87, P90 to P94 (Inside dotted-line not included) Port P50, P52, P60, P82 (Inside dotted-line included)
Direction register "1" Output Data bus Port latch
* Port P54, P56
Pull-up select Direction register "1" Output Data bus Port latch
Fig. 78 Block diagram for ports P0 to P11 in single-chip mode and E output (1)
_
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MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up select
* Port P55, P57, P95
Direction register
Data bus
Port latch
* *
Port P80 (Inside dotted-line not included.) Port P84 (Inside dotted-line included.)
Direction register
"1" "0" Output
Data bus
Port latch
CTSi
Analog output Enable D-A output
* Port P81, P85
Direction register "1" "0" Output Data bus Port latch
*E
Hold acknowledge
_
Fig. 79 Block diagram for ports P0 to P11 in single-chip mode and E output (2)
_
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IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The clock generating circuit makes basic clocks, which activate the central processing unit (CPU), bus interface unit (BIU) and internal peripheral devices, of an oscillation circuit output. Figure 82 shows the block diagram of the clock generating circuit. The clock source 1 to activate internal peripheral devices, the clock source BIU to activate the bus interface unit and the clock source CPU to activate the CPU are made of an clock input to the XIN pin. When bit 6 (clock source select bit) of processor mode register 1 is "0", the clock which is obtained by dividing an input clock to the XIN pin by 2 becomes the clock source 1. When bit 6 is "1", the clock which is an input clock to the XIN pin becomes the clock source 1 as it is. When bit 2 (clock source for peripheral devices select bit) is "0", the clock source 1 which is more divided by 2 becomes the standard clock for peripheral devices. When bit 2 is "1", the clock source 1 becomes the standard clock for peripheral devices as it is. The standard clock is more divided with the division circuit shown in Figure 82 and the clocks having all kinds of frequencies are made. Each internal peripheral device can select one of 4 clocks, Pf2, Pf16, Pf64 and Pf512, and use it. Pf2 means f(XIN), which is an oscillation circuit's frequency, divided by 2 when the clock source for peripheral devices select bit is "1". It means f(XIN) divided by 4 when that bit is "0". In the case of 1 > 12.5 MHz, fix the bit to "0". Figure 80 shows a circuit example using a ceramic (or quartz crystal) resonator. Use the manufactures' recommended values for constants such as capacitance which differs for each resonator. Figure 81 shows a circuit example inputting clocks externally. When inputting clocks externally, setting bit 1 (clock external input select bit) of particular function select register 0 (in Figure 83) to "1" makes operation of the clock oscillation circuit stop, that is, the XOUT output stays at "H", and the current consumption reduce.
XIN
XOUT
Rf
Rd
CIN
COUT
Fig. 80 Circuit example using a ceramic (or quartz crystal) resonator
XIN
XOUT Open
External clock source Vcc Vss
Fig. 81 Circuit example inputting clocks externally
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XIN XOUT Clock source for peripheral devices select bit Pf16 Pf64 1/8 1/2 1/2 1/8 1 1 0 1 Pf32 1 Watchdog timer frequency 1 select register Hold request 1/8 1/2 Wf32 1 Hold request Pf512 0 1/2 Clock source select bit 0 1/2
Pf2
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Clock external input select bit
Fig. 82 Clock generating circuit block diagram
Watchdog timer clock select bit Ready request 1/16 0 Wf512 Watchdog timer clock select bit 0 BIU Clock source for bus interface unit operation Wachdog timer CPU Clock source for CPU operation STP return select bit 1 Wachdog timer overflow signal 0
Internal clock stop select bit at WIT
Interrupt request
S
Q
STP instruction
R
Reset
S
Q
R
S
Q
Halt request to CPU from bus interface unit caused by Hold request and others
WIT instruction
R
Pfi, Wfi : Represents f(XIN) divided by i when the clock source for peripheral devices is 1. Represents f(XIN) divided by (i ! 2) when the clock source for peripheral devices is 1 divided by 2.
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
67
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MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 0
Particular function select register 0 This bit must be fixed to "0."
Address 6C16
External clock input select bit (Notes 1, 2) 0 : Actuated oscillation circuit; connecting resonator 1 : Stopped oscillation circuit; inputting externaly genarated clock Memory allocation select bit (Note 2) 0 : ROM 60 Kbytes, RAM 2048 Bytes (ROM : 00100016 to 00FFFF16, RAM : 00008016 to 00087F16) 1 : ROM 56 Kbytes, RAM 2048 Bytes (ROM:00200016 to 00FFFF16, RAM:00008016 to 00087F16) Standby state select bit 0 (Notes 1, 3) ; in execution of WIT or STP instruction in memory expansion or microprocessor mode 0 : External bus for P0 to P3, P10, P11 1 : Port Input/Output for P0 to P3, P10, P11 Standby state select bit 1 (Notes 1, 4) ; in execution of WIT or STP instruction 0 : "H" or "L" output for pins E/RD, WR 1 : "H" output for pins E/RD, WR STP rerurn select bit 0 : Wachdog timer is used when returning from Stop mode. 1 : Wachdog timer is not used when returning from Stop mode ; the maicrocomputer returns n at once. Notes 1 : After the expansion function select bit (bit 5 of particular function select register 1; Figure 62) is "1", bits 1, 5 and 6 can be written and changed. 2 : To set bits 1 and 2, continuous-twice-write operations to address 6C16 are required. 3 : When BYTE = "H" (8-bit external bus width), P11 becomes an input/output port independent of bit 5's contents. 4 : When the signal output disable select bit = "1" and bit 5 = "1", the E/RD pin outputs "L" independent of bit 6's contents in execution of WIT or STP instruction.
Fig. 83 Particular function select register 0 bit configulation
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby state. Table 7 shows the relation between standby state and each block's operation. The WIT/STP state is terminated by interrupt acceptance or reset. Accordingly, it is necessary to prepare the state in which any interrupt can be accepted before the WIT/STP instruction is executed.
STP instruction
When the STP instruction is executed, the oscillation circuit is stopped and the clock sources 1, BIU and CPU are at "L". Furthermore, "FFF16" is automatically set into the watchdog timer, and its clock source is forced to connect with Wf32 when the watchdog timer clock select bit = "0", or Pf32 when the bit = "1". This connection is cut off when the most significant bit of the watchdog timer becomes "0" or the microcomputer is reset, and the clock source is connected with the input depending on the contents of the watchdog timer frequency select register and the watchdog timer clock select bit. In STP state, all of the internal peripheral devices and the watchdog timer which use divided clocks Pf2 to Pf512, Wf32, and Wf512 are stopped. The STP state is terminated by reset or interrupt request acceptance, and then oscillation is restarted. At the same time, supply of the clock source 1 and divided clocks Pf2 to Pf512, Wf32 and Wf512 is restarted. In that condition, when the STP return select bit (bit 7 of particular function select register 0) is "0", the clock sources BIU and CPU stop at "L" until the most significant bit of the watchdog timer decremented with divided clock Pf32 or Wf32 becomes "0". However, supply of the clock sources BIU and CPU is restarted immediately after the oscillation restarts by reset. Accordingly, in this case, wait for enough time to stabilize the oscillation before the reset input of "H". Otherwise in that condition, when the STP return select bit is "1", supply of the clock sources BIU and CPU is restarted at the timing of the divided clock Pf16's "H" to "L" after the oscillation restarts. This function makes it possible to immediately return from STP state when the clock supply input to the XIN from the external is stabilized. Even though clocks are input from the external, make sure to clear the STP return select bit to "0" if the external clock is unstable for a short time when returning from STP state
WIT instruction
When the WIT instruction is executed with the internal clock stop select bit at WIT (bit 2 of particular function select register 1; Figure 62) = "0", the clock sources BIU and CPU are stopped at "L", however, the oscillation circuit, the clock source 1, and the divided clocks Pf2 to Pf512, Wf32, Wf512 are not stopped. Accordingly, although the CPU and bus interface unit stop operation, internal peripheral devices which use these divided clocks can operate even at WIT state. Otherwise, when the WIT instruction is executed with the internal clock stop select bit at WIT = "1", the oscillation circuit is not stopped, however, the clock source 1, divided clocks, and the clock sources BIU and CPU are stopped. Accordingly, in this case, all of the internal peripheral devices and the watchdog timer which use divided clocks Pf2 to Pf512, Wf32, and Wf512 are stopped. When internal peripheral devices are not used in WIT state, the latter state (internal clock stop select bit at WIT = "1") is more effective to reduce current consumption. Make sure to set the internal clock stop select bit at WIT to "1" immediately before the WIT instruction execution and clear the bit to "0" immediately after the WIT state is terminated. The WIT state is terminated when an interrupt request is accepted, and the internal clock operation is restarted. Interrupt processing can immediately be executed because oscillation circuit's operation is not stopped during WIT state.
Table 7 Relation between standby state and each block's operation. Operation at WIT/STP state Instruction Internal clock stop bit at WIT Oscillation circuit Operating (Note 1) Operating (Note 1) Stopped
1
Operating Stopped ("L") Stopped ("L")
Pf2 to Pf512 Operating Stopped ("H") Stopped ("H")
Wf2, Wf512 Operating (Note 2) Stopped ("H") Stopped ("H")
BIU, CPU
Stopped ("L") Stopped ("L") Stopped ("L")
"0" WIT "1" STP --
Internal peripheral devices using Pf2 to Pf512, Wf32, Wf512 Operation enabled (Watchdog timer operating) Operation disabled (Watchdog timer stopped) Operation disabled (Watchdog timer stopped)
Notes 1 : When the clock external input select bit is "1", the clock oscillation circuit stops. An external clock can be input. 2 : When the watchdog timer clock select bit is "1", Wf32 and Wf512 stop. The watchdog timer operates with Pf32 or Pf512.
69
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I LIM E
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle in WIT/STP
When the WIT/STP instruction is executed with the standby state select bit 1 (bit 6 of particular function select register 0) = "0", the clock sources BIU and CPU or oscillation stop without waiting for completion of the bus cycle being executed. Accordingly, the microcomputer may enter WIT/STP state during bus access in which out_ ___ ___ put of pins E, RD and WR is "L". Otherwise, when the WIT/STP instruction is executed with the standby state select bit 1 = "1", the clock sources BIU and CPU or oscillation stop after completion of read or write in the bus access cycle being executed. Consequently, in WIT/STP state, the bus be_ ___ ___ comes the nonaccess state in which output of pins E, RD and WR is "H".
Bus state in WIT/STP
Normally, pins for the address output, data input/output and bus control signal output in the memory expansion/microprocessor mode (ports P0 to P3, P10, P11 in single-chip mode; refer to section on Processor mode) retain the state as external bus pins when the clock sources BIU and CPU stop in WIT/STP state. However, when the WIT/STP instruction is executed with the standby state select bit 0 (bit 5 of particular function select register 0) = "1", those pins function depending on the contents of each port
direction register and port latch in WIT/STP state like ports in singlechip mode. That is, when setting arbitrary data to the port latch and the contents of direction register to "1", that data is output from the pin; when clearing the contents of direction register to "0", the pin becomes floating. This function makes the external bus arbitrary state in WIT/STP state. When making pins floating, take consideration with an external circuit to prevent their electric potential from becoming half level of the electric potential. When writing to registers relevant to ports P0 to P3, P10, P11 in the memory expansion/microprocessor mode, set the standby state select bit 0 to "1" before that write. If that bit is "0", write is impossible, because addresses corresponding to registers relevant to ports P0 to P3, P10, P11, which are addresses 216 to 916, 1616 to 1916, are the external memory areas shown in Figure 86. [Note] Port P11 functions as an input/output port regardless of processor modes when inputting "L" to the BYTE pin.
___
The RD pin state can arbitrarily be selected in WIT/STP state in the memory expansion/microprocessor mode, too. Refer to the Table 8 for details. Note that the function of arbitrary data output cannot be emulated using a debugger.
Table 8 Signal output disable select bit function (bit 4 of particular function select register 1; Figure 62) Processor mode Single-chip mode Pin
_ ___
Function Signal output disable select bit = "0" Outputs enable signal E.
___ ___ _
Signal output disable select bit = "1" Outputs "L".
___ ___
E/RD
___ ___
RD, WR
Outputs RD/WR when accessing internal/ external memory area. Outputs "H" or "L" after executing WIT/STP instruction Outputs "H" when standby state select bit 1 is "1".
Outputs RD/WR when accessing external memory area only. Outputs "H" or "L" after executing WIT/STP instruction. Outputs "L" when standby state select bit 0 is "1". Outputs "H" when standby state select bit 1 is "1" and standby state select bit 0 is "0."
___
RD Memory expansion mode Microprocessor mode
Outputs ALE. ALE Outputs clock 1 regardless of 1 output select bit.
Outputs "L" when multiplex bus select bit = "0". Outputs ALE when multiplex bus select bit = "1". Outputs contents of port P42 latch; necessary to set its direction register bit to "1".
Microprocessor mode
1
Note : All functions of signal output disable select bit cannot be debugged using an debugger.
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IM REL
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Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Bits 0 and 1 of processor mode register 0 (address 5E16) shown in Figure 84 are used to select any mode of the single-chip mode, the memory expansion mode and the microprocessor mode. Ports P0 to P3, P10, P11 and a part of port P4 are used as I/O pins of address, data, and control signals in the modes except the singlechip mode. Figure 85 shows the functions of ports P0 to P4, P10 and P11 in each mode. The external memory area depends on the mode. Figure 86 shows the memory map for each mode. Refer to Figure 1 for the addresses of RAM and ROM in the single-chip mode. The external memory area can be accessed in the modes except the single-chip mode. The access to the external memory is affected by the BYTE pin
* BYTE pin
When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16bit width. The data bus has a width of 16 bits when the level of the BYTE pin is "L", and ports P10 and P11 become the data I/O pins. The data bus has a width of 8 bits when level of the BYTE pin is "H", and port P10 becomes data I/O pins. Port P11 functions then as an input/output port similarly in the single-chip mode. When accessing the internal memory, the data bus always has a width of 16 bits regardless of the BYTE pin level.
7
6 0
5
4
3
2
1
0 Processor mode register 0
Address 5E16
Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. Internal memory access bus cycle select bit (Note) ; Internal memory access condition in high-speed running 0 : 2- access for internal RAM; 3- access for internal ROM and SFR 1 : 2- access for internal RAM, internal ROM and SFR Software reset bit Reset occurs when writing "1" to this bit Interrupt priority detection time select bit 0 0 : Select case 0 shown in Figure 13 0 1 : Select case 1 shown in Figure 13 1 0 : Select case 2 shown in Figure 13 Test mode bit This bit must be fixed to "0." Clock 1 output select bit 0 : No 1 output 1 : 1 output Note : Clear bit 2 to "0" in low-speed running.
Fig. 84 Processor mode register 0 bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1 0 Microprocessor mode (Note 1) Same as left
PM1 PM0 Port E/RD Mode E/RD
0 0 Single-chip mode E (Note 1)
0 1 Memory expansion mode (Note 1) E/RD RD (Note 2)
Port P0 Port P1 Port P2
E P00 to P27
E Same as left I/O port P00 to P27 Address A0 to A19, A23
E BYTE = "L" E P100 to P107 Port P10 BYTE = "H" P100 to P107 I/O port Same as left
Data (even)
* Condition except following E Same as left P100 to P107 Data (odd, even)
* When multiplex bus select bit is "1" and ___ accessing CS4 area E Same as left P100 to P107 Address Data
LA0 to LA7 (odd, even) E
BYTE = "L" Port P11 BYTE = "H"
E P110 to P117 P110 to P117 P110 to P117 E E P30 P31 I/O port P32 P33 ALE HLDA WR (Note 2) BHE Data (odd)
Same as left
I/O port
I/O port
Same as left
Port P3
P30 to P33
Same as left
E
E P40 HOLD input
Port P4
P40 to P47
I/O port
Clock 1 is output from P42 when bit 7 of processor mode register 0 is "1".
RDY input P41 P42 I/O port to P47 Clock 1 is output from P42 when bit 7 of processor mode register 0 is "1."
Clock 1 is output from P42 regardless of bit 7 of processor mode register 0 ; others are the same as left (Note 2)
Fig. 85 Processor modes and ports P0 to P4, P10 and P11
__
Notes 1 : E signal is not output in the memory expansion and microprocessor modes. __ 2 : The signal output stop disable bit (bit 4 of particular function select register 0) can stop E output in the single-chip mode and 1___ output in the micro___ processor mode. Similarly, when accessing the internal memory in the memory expansion and microprocessor modes, RD and WR output can be fixed to "H". Refer to Table 8 for details.
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor modes are explained bellow.
Memory expansion mode 216 to 916 1616 to 1916 SFR 8016 RAM
Microprocessor mode SFR
RAM
ROM
FFFFFF16
The shaded area is the external memory area.
follows during the bus cycle in which the external memory area cor___ responding to the chip select CS4 are accessed: *Output pins of addresses LA0 ___ to LA7, same as low-order addresses ___ A0 to A7, during "H" of RD or WR. ___ *Data input/output pins at even and odd addresses during "L" of RD ___ or WR. That is, it functions as a multiplex bus during that bus cycle. Port P11 has two functions depending on the level of the BYTE pin. When the BYTE pin level is "L", those pins function as data D8 to D15 I/O pins at an odd address. The I/O port function is lost. However, if an internal memory area is read, external data is not input. When the BYTE pin level is "H", port P11 functions as a programmable port P11 similarly in the single-chip mode. ___ ____ _____ Ports P30, P31, P32, and P33 become WR, BHE, ALE, and HLDA output pins respectively and lose their I/O port functions. ___ WR is a write signal which indicates a write when it is "L". ____ BHE is a byte-high-enable signal which indicates that an odd address is accessed when it is "L". Therefore, two bytes at even and odd addresses are accessed si____ multaneously when address A0 is "L" and BHE is "L". ALE is an address-latch-enable signal. The latch is open while ALE is "H", so that the address signal passes through; the address is held while ALE is "L". _____ HLDA is a hold-acknowledge signal and is used to indicate to the _____ external that the microcomputer accepts HOLD input and enters Hold state.
_____ ____
Fig. 86 External memory area for each mode
(1) Single-chip mode [00]
The microcomputer enters the single-chip mode by connecting the CNVss pin to Vss and starting from reset. Ports P0 to P4, P10 and P11 all function as normal I/O ports. Port P42 can output clock source 1 by setting bit 7 of the processor mode register 0 to "1". _ _ ___ _ In this mode, enable signal E is output from pin E/RD. Signal E output can be stopped by setting the signal output disable select bit (bit 4 of particular function select register 1) to "1", and it is possible to switch the output to "L" level. Table 8 shows the function of the signal output disable select bit's function.
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting the processor mode bits to "01" after connecting the CNVss pin to Vss and starting from reset. _ __ ___ ___ Pin E/RD becomes the RD output pin. RD is an read signal, and read is performed during it is "L" level. When the internal memory area is ___ read, the RD output can be fixed to "H" by setting the signal output disable select bit to "1". Ports P0, P1 and P2 become the output pins of addresses A0 to A19 and A23, and their I/O port function are lost. Port P10 becomes I/O pins of data D0 to D7 and loses its I/O port function. When the BYTE pin's level is "L", those pins function as data I/O pins at an even address. When the level is "H", those pins function as data I/O pins at even and odd addresses. However, if an internal memory area is read, external data is not input When the BYTE pin's level is "H" and the multiplex bus select bit (bit 5 of chip select area register; Figure 88) is "1", port P10 functions as
Ports P40 and P41 become HOLD and RDY input pins, respectively, and their I/O port function are lost. _____ HOLD is a hold-request signal. It is an input signal used to make the _____ microcomputer enter Hold state. HOLD input is accepted when the BIU has fallen from "H" to "L" level while the bus is not used. In Hold state, CPU___ at____ to A19, A23, D0 to D7, D8 to D15 (at BYTE stops "L". A0 ___ = "L"), RD, WR and BHE become floating then. These pins become _____ floating one cycle of BIU later than HLDA signal becomes "L" level. When terminating Hold state, these pins are terminated from floating _____ state one cycle of BIU later than HLDA signal becomes "H" level. ____ RDY is a ready signal. When this signal goes "L", CPU and BIU ____ stop at "L". RDY is used when a slow external memory is connected and others. Port P42 becomes a normal I/O port when bit 7 of the processor mode register 0 is "0" and becomes the clock 1 output pin when bit ____ 7 is "1". The 1 output is independent of RDY and does not stop ____ even when CPU and BIU stop owing to "L" input to the RDY pin.
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Microprocessor mode [10]
The microcomputer enters the microprocessor mode by connecting the CNVss pin to Vcc and starting from reset. It is possible to enter this mode by programming the processor mode bits to "10" after connecting the CNVss pin to Vss and starting from reset. This mode is the same as the memory expansion mode except the following: the internal ROM is disabled and an external memory is required, and clock 1 is always output from port P42 independent of bit 7 of the processor mode register 0. As shown in Table 8, 1 output can also be stopped by setting the signal output disable select bit to "1". In this case, write "1" to the port P42 direction register bit. Table 9 shows the relationship between the CNVss pin's input level and the processor modes. ___ ___ Additionally, addresses A20 to A22 or chip select signals CS0 to CS4 can be output from port P9 regardless of processor modes. For details, refer to the following sections: output function of chip select signal and address output function.
Table 9. Relationship between CNVSS pin's input levels and processor modes
CNVSS VSS Mode Description Single-chip mode upon start* Single-chip * Memory expansion ing after reset. Each mode can be selected by changing * Microprocessor the processor mode bits by software. Microprocessor mode upon * Microprocessor starting after reset.
VCC
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A IMIN
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUTPUT FUNCTION OF CHIP SELECT SIGNAL
___ ___
Ports P90 to P94 can output the chip select signals CS0 to CS4 according to the contents of chip select control register and chip select area register. Bits 0 to 3 of chip select control register select either chip select output (or addresses A20 to A22 output) or port function. Additionally, bits 0 to 2 of chip select area register select the area intended for each chip select signal. Figure 87 shows the bit configuration of chip select control register and Figure 88 shows that of chip select area register. Figure 89 shows the chip select areas. ___ ___ The bus cycle of CS3 and CS4 can be selected with bits 4 to 7 of chip select control register. That selection is valid regardless of the bus cycle select bits of processor mode register 1. Additionally, that bus ___ ___ cycle selection of ___ and CS4 is valid when selecting port function CS3 ___ with the CS3 and CS4 function select bits. When accessing addresses in which the chip select area specified by bits 0 to 2 of chip select area register and the internal memory area overlap one another, chip select signals are not output. In this case, its bus cycle is the cycle of internal memory area access. It is possible to make the chip select output floating during Hold state. That is realized by clearing the corresponding bit of port P9 direction register (address 1516) to "0" and bits 0 to 2 of waveform output mode register (address 1A16) to "000". The timing of Hold start and termination is the same as that of addresses A0 to A19. (Refer to section on processor mode.)
7
6
5
4
3
2
1
0
Address
Chip select control register 6216
CS0 function select bit (Note 1) 0 : Port P90 function 1 : CS0 output CS1, CS2 function select bit (Note 2) 0 : Port P91, P92 function 1 : CS1, CS2 output or A20, A21 output CS3 function select bit (Note 2) 0 : Port P93 function 1 : CS3 output or A22 output CS4 function select bit 0 : Port P94 function 1 : CS4 output CS3 bus cycle select bits b5 b4 In high-speed In low-speed 0 0 : 5- access Do not select. 0 1 : 4- access 4- access 1 0 : 3- access 3- access 1 1 : Do not select. 2- access CS4 bus cycle select bits b7 b6 In high-speed In low-speed 0 0 : 5- access Do not select. 0 1 : 4- access 4- access 1 0 : 3- access 3- access 1 1 : Do not select. 2- access Notes 1 : At reset, bit 0 becomes "0" when the CNVss pin's level is "L"; bit 0 becomes "1" when the CNVss pin's level is "H". 2 : Bits 6 and 7 of chip select area register (address 6316) specify whether the chip select signal or address is output.
ADDRESS OUTPUT FUNCTION
Port P91 to P93 can output the high-order addresses (A20 to A22) according to bits 1 and 2 of chip select control register, and bits 6 and 7 of chip select area register. ___ ___ ___ About signal pairs of A20 and CS1, A21 and CS2, and A22 and CS3, ___ only one signal can be output. It is because chip select signals CS1 ___ to CS3 output are common to ports P91 to P93 and addresses A20 to A22 output. It is possible to make the address output floating during Hold state. That is realized by clearing the corresponding bit of port P9 direction register (address 1516) to "0" and bits 0 to 2 of waveform output mode register (address 1A16) to "000". The timing of Hold start and termination is the same as that of addresses A0 to A19. (Refer to section on processor mode.)
Fig. 87 Chip select control register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 Chip select area register
Address 6316
Chip select area switch bits (Notes 1, 2) 000 : CS0 00100016 to 02FFFF16 (188 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 00088016 to 000DFF16 (1408 bytes) CS4 000E0016 to 000FFF16 (512 bytes) 001 : CS0 00800016 to 02FFFF16 (160 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 00088016 to 000FFF16 (1920 bytes) CS4 00100016 to 007FFF16 (28 Kbytes) 010 : CS0 00100016 to 02FFFF16 (188 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 07000016 to 077FFF16 (32 Kbytes) CS4 07800016 to 07FFFF16 (32 Kbytes) 011 : CS0 00800016 to 02FFFF16 (160 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 07000016 to 077FFF16 (32 Kbytes) CS4 07800016 to 07FFFF16 (32 Kbytes) 100 : CS0 00088016 to 02FFFF16 (190 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 08000016 to 3FFFFF16 (3.5 Mbytes) CS4 07000016 to 07FFFF16 (64 Kbytes) 101 : CS0 00088016 to 02FFFF16 (190 Kbytes) CS1 03000016 to 04FFFF16 (128 Kbytes) CS2 05000016 to 06FFFF16 (128 Kbytes) CS3 07000016 to 07FFFF16 (64 Kbytes) CS4 08000016 to 7FFFFF16 (7.5 Mbytes) 110 : CS0 00088016 to 06FFFF16 (446 Kbytes) CS1 , CS2 Not available CS3 08000016 to 3FFFFF16 (3.5 Mbytes) CS4 07000016 to 07FFFF16 (64 Kbytes) 111 : CS0 00088016 to 06FFFF16 (446 Kbytes) CS1 , CS2 Not available CS3 07000016 to 07FFFF16 (64 Kbytes) CS4 08000016 to 7FFFFF16 (7.5 Mbytes) Multiplex bus select bit (Note 1) 0 : D0 to D7 input/output (separate bus) 1 : When BYTE pin input is "H" and accessing CS4 area LA0/D0 to LA7/D7 input/output (multiplex bus) In condition except above D0 to D7 input/output (separate bus) Expansion address output select bits (Notes 1, 3) 0 0 : P91.... CS1 output, P92...CS2 output, P93...CS3 output 0 1 : P91.... A20 output, P92...CS2 output, P93...CS3 output 1 0 : P91.... A20 output, P92...A21 output, P93...CS3 output 1 1 : P91.... A20 output, P92...A21 output, P93...A22 output Notes 1 : When the expansion function select bit (bit 5 of particular function select register 1; Figure 62) is "1", bits 2, 5, 6 and 7 can be written and changed. 2 : When accessing the internal memory area, CSi is not output. When only accessing the external area, CSi output is valid. 3 : Select function of bits 6 and 7 is valid when both the CS1, CS2 function select bit and the CS3 function select bit (chip select control register) are "1".
Fig. 88 Chip select area register bit configuration
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Chip select area switch bits
Memory expansion mode Address 00 000016 00 008016
Microprocessor mode
b2, b1,b0 (000) b2,b1,b0 (001) b2,b1,b0 (011) b2, b1, b0 (100) b2, b1, b0 (101) b2, b1, b0 (110) b2, b1, b0 (111) b2,b1,b0 (010)
Fig. 89 Chip select areas
00 088016 00 0C8016 00 0E0016 00 100016 CS3 (1408 bytes) CS4(512 bytes) CS3 (1920 bytes) CS4 (28 Kbytes) 00 800016 CS0 (188 Kbytes) CS0 (188 Kbytes) CS0 (160 Kbytes) CS0 (160 Kbytes) 01 000016 02 000016 03 000016 CS1 (128 Kbytes) CS1 (128 Kbytes) CS1 (128 Kbytes) CS1 (128 Kbytes) CS1 (128 Kbytes) CS2 (128 Kbytes) CS2 (128 Kbytes) CS3 (32 Kbytes) CS4 (32 Kbytes) CS2 (128 Kbytes) CS3 (32 Kbytes) CS4 (32 Kbytes) CS2 (128 Kbytes) CS2 (128 Kbytes) 05 000016 07 000016 07 800016 08 000016 10 000016 20 000016 40 000016 80 000016 FF FFFF16 CS3 (3.5 Mbytes) CS3 (3.5 Mbytes) CS4 (7.5 Mbytes) CS1 (128 Kbytes) CS2 (128 Kbytes) CS3 (64 Kbytes) CS4 (64 Kbytes) CS3 (64 Kbytes) CS0 (190 Kbytes) CS0 (190 Kbytes) CS0 (446 Kbytes) CS0 (446 Kbytes) CS4 (64 Kbytes) CS4 (7.5 Mbytes) Note : When the area inteded for chip select signal output and the internal memory area (ROM, RAM, SFR) overlap one another, the bus access cycle of internal memory area is used. The chip select output does not become active for that internal memory area.
SFR
SFR
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Internal RAM 2048 bytes
Internal RAM 2048 bytes
RY
Internal ROM 60 Kbytes
External memory area
Out of area intended for chip select signal output
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
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IM REL
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Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MEMORY MODIFICATION FUNCTION
The M37754M8C-XXXGP's internal memory size and address area can be modified by set of bit 2 (memory allocation select bit) of the particular function select register 0. Figure 90 shows the memory allocation when modifying the internal memory area.
When ordering a mask ROM, Mitsubishi Electric corp. produces the mask ROM using the data within 60 Kbytes (between addresses 00100016 to 00FFFF16). It is regardless of the selected ROM size (refer to MASK ROM ORDER CONFIRMATION FORM). Therefore, on the EPROM tendered for ordering a mask ROM, program data "FF16" to addresses which correspond to the area out of the selected ROM area. Additionally, address 00FFFF16 of the microcomputer corresponds to the lowest address of the tendered EPROM.
Memory allocation select bit = "0" ROM size : 60 Kbytes RAM size : 2048 bytes 00 000016 SFR 00 008016 Internal RAM 2048 bytes 00 087F16 00 100016
Memory allocation select bit = "1"
ROM size : 56 Kbytes RAM size : 2048 bytes 00 000016 SFR 00 008016 Internal RAM 2048 bytes 00 087F16 00 200016
Internal ROM 60 Kbytes
Internal ROM 56 Kbytes
00 FFFF16
00 FFFF16
External memory area
External memory area
FF FFFF16
FF FFFF16
Note : The internal ROM area becomes external memory area in microprocessor mode.
Fig. 90 Memory allocation when modifying internal memory area with memory allocation select bit
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES AND INSTRUCTION SET
The M37754M8C-XXXGP and M37754M8C-XXXHP have 29 powerful addressing modes; 1 addressing mode is added to the basis of the 7700 series. Refer to the "7751 Series Software Manual" for the details.
INSTRUCTION SET
The M37754M8C-XXXGP and M37754M8C-XXXHP have the extended instruction set; 6 instructions are added to the instruction set of 7700 series. The object code of this extended instruction set is upwards compatible to that of 7700 series instruction set. Refer to the "7751 Series Software Manual" for the details.
SHORTENING NUMBER OF INSTRUCTION EXECUTION CYCLES
Shortening number of instruction execution cycles is realized in the M37754M8C-XXXGP and M37754M8C-XXXHP owing to modifications of the instruction execution algorithm and the CPU circuit, and others. Refer to the "7751 Series Software Manual" about the number of instruction execution cycles.
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders: <M37754M8C-XXXGP> (1) M37754M8C-XXXGP mask ROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets) (1) M37754M8C-XXXHP mask ROM order confirmation form (2) 100P6Q mark specification form (3) ROM data (EPROM 3 sets)
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC AVCC VI VI Parameter Power source voltage Analog power source voltage Input voltage RESET, CNVSS, BYTE Input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, VREF, XIN Output voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XOUT, E Power dissipation Operating temperature Storage temerature Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 -0.3 to VCC+0.3 Unit V V V V
VO Pd Topr Tstg
-0.3 to VCC+0.3 300 -20 to 85 -40 to 150
V mW C C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V10 %, Ta = -20 to 85 C, unless otherwise noted)
Symbol VCC AVCC VSS AVSS VIH VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOH(avg) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage High-level input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, XIN, ______ RESET, CNVSS, BYTE High-level input voltage P100-P107, P110-P117 (in single-chip mode) High-level input voltage P100-P107, P110-P117 (in memory expansion mode and microprocessor mode) Low-level input voltage P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, XIN, ______ RESET, CNVSS, BYTE Low-level input voltage P100-P107, P110-P117 (in single-chip mode) Low-level input voltage P100-P107, P110-P117 (in memory expansion mode and microprocessor mode) High-level peak output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P92, P95, P100-P107, P110-P117 P93, P94 High-level average output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P92, P95, P100-P107, P110-P117 P93, P94 Low-level peak output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P54-P57, P60-P67, P70-P77, P80-P87, P90, P95, P100-P107, P110-P117 P50-P53, P91-P94 Low-level average output current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P54-P57, P60-P67, P70-P77, P80-P87, P90, P95, P100-P107, P110-P117 P50-P53,P91-P94 External clock frequency input (Note 3) Low-speed running High-speed running Limits Min. 4.5 Typ. 5.0 VCC 0 0 Max. 5.5 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA MHz
0.8 VCC 0.8 VCC 0.5 VCC 0 0 0
VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC -10 -20 -5 -15 10 20 5 15 25 40
Notes 1: Average output current is the averaage value of a 100 ms interval. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P9 must be 110 mA or less, the sum of IOH(peak) for ports P4, P5, P6, P7, and P9 must be 80 mA or less. 3: When the clock source select bit is "1," f(XIN)'s maximum limit is 12.5 MHz at low-speed running and is 20 MHz at high-speed running.
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz (Note))
Symbol Parameter Test conditions Min. Limits Typ. Max. Unit
VOH
VOH VOH VOH
VOL
VOL VOL VOL VT+ --VT-
High-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P40-P47, P50-P57, P60-P67, P70-P77, IOH = -10 mA P80-P87, P90-P92, P95, P100-P107, P110-P117 High-level output voltage P00-P07, P10-P17, P20-P23, IOH = -400 A P27, P31, P33, P90-P92, P100-P107, P110-P117 _ High-level output voltage E, P30, P32 IOH = -10 mA IOH = -400 A IOH = -15 mA High-level output voltage P93, P94 IOH = -600 A Low-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P40-P47, P54-P57, P60-P67,P70-P77, IOL = 10 mA P80-P87, P90, P95, P100-P107, P110-P117 Low-level output voltage P00-P07, P10-P17, P20-P23, P27, P31, P33, P90, IOL = 2 mA P100-P107, P110-P117 Low-level output voltage E, P30, P32 Low-level output voltage P50-P53, P91-P94
_____ ____ _
3.4
V
4.8 3.4 4.8 3.4 4.8
V
V V
2
V
0.45 1.6 0.4 2 0.4 0.4 0.2 0.1 1
V V V
IOL IOL IOL IOL
= 10 mA = 2 mA = 20 mA = 2 mA
Hysteresis
VT+ --VT- VT+ --VT-
Hysteresis
HOLD, RDY, TA0IN-TA4IN,_____ ____ ____ TB0IN-TB2IN, INT0-INT4, ADTRG, ____ ____ CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 ______ _____ ____ RESET, HOLD, RDY
V V V
IIH
IIL
IIL VRAM
Hysteresis XIN High-level input current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XIN, RESET, CNVSS, BYTE Low-level input current P00-P07, P10-P17, P20-P23, P27, P30-P33, P40-P47, P50-P53, P60-P67, P70-P77, P80-P87, P90-P95, P100-P107, P110-P117, XIN, RESET, CNVSS, BYTE Low-level input current P54-P57, P95 RAM hold voltage Power supply current (target value)
0.5 0.3
VI = 5 V
5
A
VI = 0 V
-5
A
ICC
VI = 0 V, No pull-up transistor -0.25 VI = 0 V, Pull-up transistor used 2 When clock is stoped. Output-only pin is f(XIN) = 40 MHz, square waveform (Note) open and other pins are Vss during Ta = 25 C when clcock is stopped. reset. Ta = 85 C when clcock is stopped.
-0.5
-5 -1.0 50 1
A mA V
mA
25
A
20
Note: f(XIN) = 20 MHz when the clock source select bit = "1."
81
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V 10 %, VSS = AVSS = 0 V, Ta = -20 to 85 C, the clock source select bit = 0, unless otherwise noted) Symbol ---------- Parameter Resolution VREF = VCC Test conditions A-D converter selected Comparator selected 10-bit mode 250 kHz AD 8-bit mode 12.5 MHz Comparator 250 kHz AD 8-bit mode 20 MHz (Note 1) Comparator 10-bit mode 8-bit mode Comparator 8-bit mode Comparator 10-bit mode 8-bit mode Comparator 5 5.9 4.9 1.4 2.45 0.7 4.72 3.92 1.12 2.7 0 Limits Typ. Unit Bits V LSB LSB mV LSB mV k
Min.
----------
Absolute accuracy
VREF = VCC
RLADDER
Ladder resistance
VREF = VCC
Max. 10 1 256 VREF 3 2 40 3 60 20
tCONV
Conversion time
AD = f(XIN)/4 High-speed selected running (f(XIN) 40 MHz) AD = f(XIN)/2 (Note 2) selected
Low-speed running (f(XIN) 25 MHz) (Note 2)
s
VREF VIA
Reference voltage Analog input voltage
VCC VREF
V V
Notes 1: This is valid when the high-speed running is selected. 2: When the clock source select bit = 1, f(XIN) is 20 MHz or less at the high-speed running, and f(XIN) is 12.5 MHz or less at the low-speed running.
D-A CONVERTER CHARACTERISTICS
(VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---- ---- tsu RO IVREF Parameter Resolution Absolute accuracy Set time Output resistance Reference power supply input current Test conditions Limits Typ. Unit Bits % s k mA
Min.
1 (Note)
2.5
Max. 8 1.0 3 4 3.2
Note: The test conditions are as follows: * One D-A converter is used. * The D-A register value of the unused D-A converter is "0016." * The reference power supply input current of the ladder resistance of the A-D converter is excluded.
82
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V10 %, VCC = 0 V, Ta = -20 to 85 C, unless otherwise noted)
If the values depends on external clock frequency f(XIN), formulas of the limits are shown below. Also, the values at f(XIN) = 40 MHz in high
speed running and at f(XIN) = 25 MHz in low-speed running are shown in ( ). At this time, the clock source select bit is "0." When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN). The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Timer A input (Count input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 40 40 Max. Unit ns ns ns
Timer A input (Gating input in timer mode)
Symbol Parameter f(XIN) 40 MHz tc(TA) TAiIN input cycle time (XIN) 25 MHz f(XIN) 40 MHz tw(TAH) TAiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TAL) TAiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 8 x 10 9 (320) f(XIN) 8 x 10 9 (200) f(XIN) 9 4 x 10 (160) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 10 9 f(XIN) (160) Max. Unit ns ns ns ns ns ns
Note : The TAiIN input cycle time requires 4 or more cycles of count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0."
Timer A input (External trigger input in one-shot pulse mode)
Symbol Parameter f(XIN) 40 MHz tc(TA) TAiIN input cycle time f(XIN) 25 MHz Limits Min. 8 x 10 9 (200) f(XIN) 9 4 x 10 (160) f(XIN) 80 80 Max. Unit ns ns ns ns
tw(TAH) tw(TAL)
TAiIN input high-level pulse width TAiIN input low-level pulse width
Timer A input (External trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 80 Max. Unit ns ns
Timer A input (Up-down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
83
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input (Two-phase pulse input in event counter mode)
Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 800 200 200 Max. Unit ns ns ns
* Count input in event counter mode * Gating input in timer mode * External trigger input in one-shot pulse mode * External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) * Up-down and count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL)
TAiOUT input (Up-down input)
th(TIN-UP) tsu(UP-TIN)
TAiIN input (When count by falling) TAiIN input (When count by rising)
* Two-phase pulse input in event counter mode
tc(TA)
TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Test conditions * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns
Timer B input (Pulse period measurement mode)
Symbol Parameter f(XIN) 40 MHz tc(TB) TBiIN input cycle time f(XIN) 25 MHz f(XIN) 40 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 9 8 x 10 (320) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 10 9 (160) f(XIN) 8 x 10 9 (200) f(XIN) 9 4 x 10 (160) f(XIN) Max. Unit ns ns ns ns ns ns
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(X IN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0."
Timer B input (Pulse width measurement mode)
Symbol Parameter f(XIN) 40 MHz tc(TB) TBiIN input cycle time f(XIN) 25 MHz f(XIN) 40 MHz tw(TBH) TBiIN input high-level pulse width f(XIN) 25 MHz f(XIN) 40 MHz tw(TBL) TBiIN input low-level pulse width f(XIN) 25 MHz Limits Min. 16 x 109 (400) f(XIN) 8 x 10 9 (320) f(XIN) 8 x 10 9 (200) f(XIN) 9 4 x 10 (160) f(XIN) 9 8 x 10 (200) f(XIN) 4 x 10 9 (160) f(XIN) Max. Unit ns ns ns ns ns ns
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running (f(XIN) 40 MHz) and when the count source is f(X IN)/2 in low-speed running (f(XIN) 25 MHz). At this time, the clock source select bit is "0."
A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width Limits Min. 1000 125 Max. Unit ns ns
85
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Parameter Limits Min. 200 100 100 0 20 90 Max. Unit ns ns ns ns ns ns ns
80
External interrupt INTi input
Symbol tw(INH) tw(INL) INTi input high-level pulse width INTi input low-level pulse width Parameter Limits Min. 250 250 Max. Unit ns ns
tc(TB) tw(TBH) TBiIN input tw(TBL)
tc(AD) tw(ADL) ADTRG input
tc(CK) tw(CKH) CLKi tw(CKL) th(C - Q) TxDi td(C - Q) RxDi tw(INL) tsu(D - C) th(C - D)
INTi input Test conditions * Vcc = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V,VOH = 2.0 V,CL = 100 pF
tw(INH)
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless
otherwise noted) The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Symbol Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Limits Min. 42 42 0 0 Max. Unit ns ns ns ns
tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD)
: f(XIN) = 20 MHz when the clock source select bit = "1".
Switching characteristics
Symbol td(1-HLDA) tpxz(HLDA-RDZ) tpxz(HLDA-WRZ) tpxz(HLDA-BHEZ) tpxz(HLDA-AZ) tpxz(HLDA-DLZ/DHZ) tpzx(HLDA-RDZ) tpzx(HLDA-WRZ) tpzx(HLDA-BHEZ) tpzx(HLDA-AZ) tpzx(HLDA-DLZ/DHZ)
(VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless otherwise noted) Parameter Limits Min. Max. 50 50 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns
: f(XIN) = 20 MHz when the clock source select bit = "1".
HLDA output delay time Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating start delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state) Floating release delay time (at hold state)
0 0 0 0 0
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RDY input (when 3- access in high-speed running)
1
RD,WR
RDY input tsu(RDY-1) th(1-RDY)
V RDY input is always sampled at the falling edge of 1 just before the RD and WR signals' rise regardless of the bus mode and the number of waits.
HOLD input
1 tsu(HOLD-1)
th(1-HOLD)
HOLD input td(1-HLDA) td(1-HLDA)
HLDA output tpxz(HLDA-RDZ) Hi-Z RD tpzx(HLDA-WRZ) Hi-Z WR tpzx(HLDA-RDZ)
tpxz(HLDA-WRZ)
tpxz(HLDA-BHE) Hi-Z BHE output
tpzx(HLDA-BHE)
tpxz(HLDA-AZ) A0-A7 output A8-A15 output A16-A23 output tpxz(HLDA-DLZ/DHZ) D0-D7 output D8-D15 output (BYTE ="L") Hi-Z Hi-Z
tpzx(HLDA-AZ)
tpzx(HLDA-DLZ/DHZ)
Test conditions * VCC = 5 V10 % * RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V * HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
88
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0"V, unless
otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Single-chip mode Symbol tc tw(H) tw(L) tr tf tsu(PiD-E) th(E-PiD) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time Port Pi input setup time (i = 0--11) Port Pi input hold time (i = 0--11) Limits Min. Max. 25 tc/2 - 8 tc/2 - 8 8 8 60 0 Unit ns ns ns ns ns ns ns
V: f(XIN) = 20 MHz when the clock source select bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 50 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. Switching characteristics (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0"V, unless otherwise noted) (Single-chip mode) Symbol td(E-PiQ) Parameter Port Pi data output delay time (i = 0--11) Limits Min. Max. 60 Unit ns
V: f(XIN) = 20 MHz when the clock source select bit = "1"
tr f(XIN)
tf
tc
tw(H)
tw(L)
E td(E - PiQ) Port Pi output (i = 0--11) tsu(PiD - E) Port Pi input (i = 0--11) Test conditions * VCC = 5 V10 % * Intput timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF th(E - PiD)
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz when the clock source select bit = "0", unless
otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Memory expansion and Microprocessor mode : Low-speed running Symbol tc tw(H) tw(L) tr tf tsu(DH-RD) tsu(DL-RD) tsu(PiD-RD) th(RD-DH) th(RD-DL) th(RD-PiD) tsu(A-DL/DH) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time High-order data input setup time (BYTE = "L") Low-order data input setup time Port Pi input setup time (i = 4--9, 11) High-order data input hold time (BYTE = "L") Low-order data input hold time Port Pi input hold time (i = 4--9, 11) Data setup time with address stabilized (Note 3) Limits Unit Min. Max. 40 ns tc/2 - 8 ns tc/2 - 8 ns 8 ns 8 ns 30 ns 30 ns 60 ns 0 ns 0 ns 0 ns 60 (2- access) 140 (3- access) ns 220 (4- access) 60 (2- access) 140 (3- access) ns 220 (4- access) 55 (2- access) 135 (3- access) ns 215 (4- access)
tsu(CS-DL/DH)
Data setup time with chip select stabilized (Note 3)
tsu(LA-DL)
Data setup time with address stabilized (Note 3)
: f(XIN) = 12.5 MHz when the clock source selet bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 80 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. 3: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the page after the next page.
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz when the clock source select bit = "0",
unless otherwise noted) Memory expansion and Microprocessor mode : Low-speed running Symbol tw(H), tw(L) td(1-WR) td(1-RD) __ tw(WR) __ tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) th(WR-BHE) th(RD-BHE) th(WR-CS) th(RD-CS) th(WR-DLQ/DHQ) tpzx(WR-DLZ/DHZ) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tpxz(RD-DLZ) tpzx(RD-DLZ) td(WR-PiQ) Parameter 2- access Min. Max. 20 -7 12 -7 12 60 60 15 15 8 15 15 8 15 15 8 35 30 4 4 22 10 10 10 10 10 10 15 0 12 12 5 9 5 18 60 3- access 4- access Min. Max. Min. Max. 20 20 -7 12 -7 12 -7 12 -7 12 140 140 140 140 15 95 15 95 8 55 15 95 15 95 8 55 15 95 15 95 8 55 35 35 30 30 4 4 4 4 22 62 10 10 10 10 10 10 10 10 10 10 10 10 15 15 0 0 12 92 12 92 5 52 9 25 (Note) 5 5 18 18 60 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
high-level pulse width, low-level pulse width (Note) ___ WR output delay time __ RD output delay time ___ WR low-level pulse width (Note) RD low-level pulse width (Note) Address output delay time (Note) Address output delay time (Note) Address output delay time (Note) ____ BHE output delay time (Note) ____ BHE output delay time (Note) ____ BHE output delay time (Note) Chip select output delay time (Note) Chip select output delay time (Note) Chip select output delay time (Note) Data output delay time Floating start delay time (Note) ALE output delay time ALE output delay time ALE pulse width (Note) Address hold time (Note) Address hold time (Note) BHE hold time (Note) BHE hold time (Note) Chip select hold time (Note) Chip select hold time (Note) Data hold time (Note) Floating release delay time Address output delay time (Note) Address output delay time (Note) Address output delay time (Note) Address hold time Floating start delay time Floating release delay time (Note) Port Pi data output delay time (i = 4--9, 11)
: f(XIN) = 12.5 MHz when the clock source selet bit = "1" Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page.
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. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
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MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
Memory expansion and Microprocessor mode : Low-speed running (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 25 MHz when the clock source select bit = "0", unless otherwise noted) Symbol tsu(A-DL/DH) tsu(CS-DL/DH) tw(H), tw(L) tw(WR), tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) tsu(LA-DL) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tpzx(RD-DLZ)
__ __
Parameter Data setup time with address stabilized Data setup time with chip select stabilized
2- access 3 x 109 f(XIN) 3 x 109 f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 3 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) - 60 - 60 - 20 - 20 - 25 - 25 - 32 - 25 - 25 - 32 - 25 - 25 - 32 - 18 - 30 - 30 - 30 - 30 - 30 - 30 - 25 - 10 - 65 - 28 - 28 - 35
3- access 5 x 109 f(XIN) - 60 5 x 109 f(XIN) - 60
4- access 7 x 109 f(XIN) - 60 7 x 109 f(XIN) - 60
Unit ns ns ns
high-level pulse width, f low-level pulse width
___ ___
WR, RD low-level pulse width Address output delay time Address output delay time Address output delay time
____
4x f(XIN) - 20 109 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) - 25 - 25 - 65 - 25 - 25 - 65 - 25 - 25 - 65 - 18
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
BHE output delay time
____
BHE outupt delay time
____
BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time ALE pulse width Address hold time Address hold time
____
BHE hold time
____
BHE hold time Chip select hold time Chip select holt time Data hold time Floating start delay time Data setup time with address stabilized Address output delay time Address output delay time Address output delay time Address hold time Floating release delay time
5x - 65 f(XIN) 109
7x f(XIN) 3 x 109 f(XIN) 3 x 109 f(XIN) 2 x 109 f(XIN) 1 x 109 f(XIN) 109
- 65 - 28 - 28 - 28 - 15
ns ns ns ns ns ns
V: f(XIN) 12.5 MHz when the clock source select bit = "1" Note: When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN).
1x f(XIN) - 22 109
92
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 2- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H)
tr
tf
tc
td(1-WR)
td(1-WR)
RD
WR tw(WR) tw(ALE) ALE output td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0 to A7 output A8 toA15 output A16 toA23 output td(A-ALE) td(CS-WR) CS0 to CS4 output td(CS-ALE) td(WR-DLQ/DHQ) Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
th(WR-DLQ/DHQ) D0 to D7 output D8 to D15 output (BYTE = "L") Hi-Z Output data tpxz(WR-DLZ/DHZ) tpzx(WR-DLZ/DHZ) td(LA-WR) D0/LA0 to D7/LA7 output (multiplex bus (Note)) Address th(ALE-LA) td(LA-ALE) td(WR-PiQ) Port Pi output td(WR-DLQ) Data th(WR-DLQ)
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (Port Pi, f(XIN)) Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Data input : VIL = 0.8 V, VIH = 2.5 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
93
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 2- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc
RD tw(RD)
WR tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") Hi-Z tsu(DL/DH-RD) Input data Chip select Address
th(RD-BHE)
th(RD-A)
th(RD-CS)
th(RD-DL/DH)
td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) td(LA-ALE) D0--D7 input (multiplex bus (Note)) Address
tpxz(RD-DLZ)
tpzx(RD-DLZ)
th(ALE-LA) tsu(LA-DL)
tsu(DL-RD) th(RD-DL) Data
tsu(PiD-RD) Port Pi input Input data
th(RD-PiD)
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V
94
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc
RD
WR tw(WR) tw(ALE) ALE output
td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) td(LA-ALE) Address th(ALE-LA) Output data tpzx(WR-DLZ/DHZ) td(WR-DLQ) Data
th(WR-DLQ/DHQ)
tpxz(WR-DLZ/DHZ) th(WR-DLQ)
td(WR-PiQ) Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied: *BYTE = "H" *Multiplex bus select bit = "1" *While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
95
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc
RD tw(RD) WR
tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output Address td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(CS-DL/DH) tsu(A-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) tsu(DL-RD) tsu(LA-DL) Data tpxz(RD-DLZ) tsu(DL/DH-RD) Input data Chip select
th(RD-BHE)
th(RD-A)
th(RD-CS)
th(RD-DL/DH)
tpzx(RD-DLZ)
th(RD-DL)
tsu(PiD-RD) Port Pi input Input data
th(RD-PiD)
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
96
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc
RD
WR tw(WR) tw(ALE) ALE output
td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0-A7 output A8-A15 output A16-A23 output td(A-ALE) td(CS-WR) CS0-CS4 output td(CS-ALE) Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
td(WR-DLQ/DHQ) D0-D7 output D8-D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) Output data
th(WR-DLQ/DHQ)
tpxz(WR-DLZ/DHZ)
td(LA-WR) D0/LA0-D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE)
td(WR-DLQ) Data th(ALE-LA)
th(WR-DLQ)
td(RD-PiQ) Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
97
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4- access in low-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-RD) td(1-RD) tr tf tc
RD tw(RD) WR
tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) Chip select Address
th(RD-BHE)
th(RD-A)
th(RD-CS)
tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE ="L") td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) Address td(LA-ALE) D0--D7 input (multiplex bus (Note)) th(ALE-LA) tsu(LA-DL) tsu(DL-RD) th(RD-DL) Data tpxz(RD-DLZ) tpzx(RD-DLZ) tsu(DL/DH-RD) Input data th(RD-DL/DH)
tsu(PiD-RD) Port Pi input Input data
th(RD-PiD)
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
98
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN)=40 MHz when the clock source select bit = "0", unless
otherwise noted) V The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. Memory expansion and Microprocessor mode : High-speed running Symbol tc tw(H) tw(L) tr tf tsu(DH-RD) tsu(DL-RD) tsu(PiD-RD) th(RD-DH) th(RD-DL) th(RD-PiD) tsu(A-DL/DH) Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time High-order data input setup time (BYTE = "L") Low-order data input setup time Port Pi input setup time (i = 4--9, 11) High-order data input hold time (BYTE = "L") Low-order data input hold time Port Pi input hold time (i = 4--9, 11) Data setup time with address stabilized (Note 3) Limits Min. 25 tc/2 - 8 tc/2 - 8 Max. Unit ns ns ns ns ns ns ns ns ns ns ns access) access) access) access) access) access) access) access) access) ns
8 8 30 30 60 0 0 0 65 (3- 110 (4- 160 (5- 65 (3- 110 (4- 160 (5- 50 (3- 100 (4- 150 (5-
tsu(CS-DL/DH)
Data setup time with chip select stabilized (Note 3)
ns
tsu(LA-DL)
Data setup time with address stabilized (Note 3)
ns
: f(XIN) = 20 MHz when the clock source selet bit = "1" Notes 1: When the clock source select bit = "1", tc's minimum limit is 50 ns. 2: When the clock source select bit = "1", set tw(H)/tc and tw(L)/tc ratios to 45 to 55 %. 3: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the page after the next page.
99
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics
(VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 40 MHz when the clock source select bit = "0", unless otherwise noted) Memory expansion and Microprocessor mode : High-speed running Symbol tw(H), tw(L) td(1-WR) td(1-RD) __ tw(WR) __ tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) th(WR-BHE) th(RD-BHE) th(WR-CS) th(RD-CS) th(WR-DLQ/DHQ) tpzx(WR-DLZ/DHZ) td(LA-WR) td(LA-RD) td(LA-ALE) th(ALE-LA) tPXZ(RD-DLZ) tPZX(RD-DLZ) td(WR-PiQ) Parameter 3- access Min. Max. 5 -7 12 -7 12 55 55 25 25 10 25 25 10 25 25 10 35 30 4 4 10 10 10 10 10 10 10 15 0 15 15 5 10 5 15 60 4- access Min. Max. 5 -7 12 -7 12 80 80 45 45 35 45 45 35 45 45 35 35 30 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 5 15 60 5- access Min. Max. 5 -7 12 -7 12 130 130 45 45 35 45 45 35 45 45 35 35 30 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 5 15 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
: f(XIN) = 20 MHz when the clock source selet bit =
high-level pulse width, low-level pulse width ___ WR output delay time ___ RD output delay time ___ WR low-level pulse width ___ RD low-level pulse width Address output delay time Address output delay time Address output delay time ____ BHE output delay time ____ BHE output delay time ____ BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time Data output delay time Floating start delay time ALE output delay time ALE output delay time ALE pulse width Address hold time Address hold time ____ BHE hold time ____ BHE hold time Chip select hold time Chip select hold time Data hold time Floating release delay time Address output delay time Address output delay time Address output delay time Address hold time Floating start delay time Floating release delay time Port Pi data output delay time (i = 4--9, 11)
(Note)
(Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
(Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
"1" Note: Since the values depend on external clock frequency f(XIN), calculate them by using the bus timing data formulas on the next page.
100
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
Memory expansion and Microprocessor mode : High-speed running (VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 40 MHz when the clock source select bit = "0", unless otherwise noted) Symbol tsu(A-DL/DH) tsu(CS-DL/DH) tw(H), tw(L) tw(WR), tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) tpxz(WR-DLZ/DHZ) tsu(LA-DL) td(LA-WR) td(LA-RD) td(LA-ALE) td(ALE-LA) tpzx(RD-DLZ)
__ __
Parameter Data setup time with address stabilized Data setup time with chip select stabilized
3- access 5 x 10 9 f(XIN) 5 x 10 9 f(XIN) 1 x 10 9 f(XIN) 3 x 10 9 f(XIN) 2 x 10 9 f(XIN) 2 x 10 9 f(XIN) 1 x 10 9 f(XIN) 2 x 10 9 f(XIN) 2 x 10 9 f(XIN) 1 x 10 9 f(XIN) 2 x 10 9 f(XIN) 2 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 5 x 10 9 f(XIN) 2 x 10 9 f(XIN) 2 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) 1 x 10 9 f(XIN) - 60 - 60 - 20 - 20 - 25 - 25 - 15 - 25 - 25 - 15 - 25 - 25 - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 10 +5
4- access 7 x 10 9 f(XIN) - 65 7 x 10 9 f(XIN) - 65
5- access 9 x 10 9 f(XIN) - 65 9 x 10 9 f(XIN) - 65
Unit ns ns ns
high-level pulse width, low-level pulse width
___ ___
WR, RD low-level pulse width Address output delay time Address output delay time Address output delay time
____
BHE outuput delay time
____
BHE outuput delay time
____
BHE outuput delay time Chip select output delay time Chip select output delay time Chip select output delay time ALE pulse width Address hold time Address hold time
____
4 f(XIN) 3 x 10 9 f(XIN) 3 x 10 9 f(XIN) 2 x 10 9 f(XIN) 3 x 10 9 f(XIN) 3 x 10 9 f(XIN) 2 x 10 9 f(XIN) 3 x 10 9 f(XIN) 3 x 10 9 f(XIN) 2 x 10 9 f(XIN) 2 x 10 9 f(XIN)
x 10 9
- 20 - 30 - 30 - 15 - 30 - 30 - 15 - 30 - 30 - 15 - 15
6 f(XIN)
x 10 9
- 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
BHE hold time
____
BHE hold time Chip select hold time Chip select hold time Data hold time Floating start delay time Data setup time with address stabilized Address outuput delay time Address outuput delay time Address outuput delay time Address hold time Floating release delay time
7x f(XIN) 3 x 109 - 35 f(XIN) 3 x 109 - 35 f(XIN) 2 x 109 - 20 f(XIN) - 75 109 - 15 - 10
- 75 - 35 - 35 - 20
9x - 75 f(XIN) 109
ns ns ns ns ns ns
V: f(XIN) 20 MHz when the clock source select bit = "1" Note: When the clock source select bit is "1", regard f(XIN) in tables as 2*f(XIN).
101
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H)
tr
tf
tc
td(1-WR)
td(1-WR)
RD
WR tw(WR) tw(ALE) ALE output td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
td(CS-ALE) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") Output data tpzx(WR-DLZ/DHZ) tpxz(WR-DLZ/DHZ) th(WR-DLQ/DHQ)
td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) td(LA-ALE) Address
td(WR-DLQ) th(WR-DLQ) Data th(ALE-LA)
td(WR-PjQ) Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
102
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 3- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H)
tr
tf
tc
td(1-RD)
td(1-RD)
RD tw(RD) WR
tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") tpxz (RD-DLZ) td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) tsu(DL/DH-RD) Input data Chip select Address
th(RD-BHE)
th(RD-A)
th(RD-CS)
th(RD-DL/DH)
tpzx(RD-DLZ) Address td(LA-ALE) th(ALE-LA) tsu (LA-DL) Data tsu(DL-RD) th(RD-DL)
tsu(PiD-RD) Port Pi input Input data
th(RD-PiD)
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
103
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc
RD
WR tw(WR) tw(ALE) ALE output td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) td(WR-DLQ) td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) Data Output data
th(WR-DLQ/DHQ)
tpxz(WR-DLZ/DHZ)
th(WR-DLQ)
td(WR-PiQ) Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
104
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 4- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw (H) tr tf tc
td(1-RD)
td(1-RD)
RD tw(RD) WR
tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output Address td(A-ALE) td(CS-RD) CS0-CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0-D7 input D8-D15 input (BYTE = "L") tpxz(RD-DLZ) td(LA-RD) LA0-LA7 output (D0/LA0-D7/LA7) (multiplex bus (Note)) Address td(LA-ALE) D0-D7 input (multiplex bus (Note)) th(ALE-LA) tsu(LA-DL) Data tsu(DL-RD) tsu(DL/DH-RD) Input data Chip select
th(RD-BHE)
th(RD-A)
th(RD-CS)
th(RD-DL/DH)
tpzx(RD-DLZ)
th(RD-DL)
tsu(PiD-RD) Port Pi input Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Input data
th(RD-PiD)
Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
105
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 5- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H) td(1-WR) td(1-WR) tr tf tc
RD
WR tw(WR) tw(ALE) ALE output td(ALE-WR)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Chip select Address
th(WR-BHE)
th(WR-A)
th(WR-CS)
th(WR-DLQ/DHQ) td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") tpzx(WR-DLZ/DHZ) tpxz(WR-DLZ/DHZ) td(WR-DLQ) td(LA-WR) D0/LA0--D7/LA7 output (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) Data th(WR-DLQ) Output data
td(WR-PiQ) Port Pi output
Note: These become a multiplex bus only when all of the following conditions are satisfied: * BYTE = "H" * Multiplex bus select bit = "1" * While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
106
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(when 5- access in high-speed running )
tw(H) tw(L) f(XIN) tw(L) 1 tw(H)
tr
tf
tc
td(1-RD)
td(1-RD)
RD tw(RD) WR
tw(ALE) ALE output
td(ALE-RD)
td(BHE-RD) BHE output td(BHE-ALE) td(A-RD) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-RD) CS0--CS4 output td(CS-ALE) tsu(CS-DL/DH) tsu(A-DL/DH) D0--D7 input D8--D15 input (BYTE = "L") tpxz(RD-DLZ) td(LA-RD) LA0--LA7 output (D0/LA0--D7/LA7) (multiplex bus (Note)) D0--D7 input (multiplex bus (Note)) Address td(LA-ALE) th(ALE-LA) tsu(LA-DL) Chip select Address
th(RD-BHE)
th(RD-A)
th(RD-CS)
tsu(DL/DH-RD) Input data
th(RD-DL/DH)
tpzx(RD-DLZ)
tsu(DL-RD) th(RD-DL) Data
tsu(PiD-RD) Port Pi input Input data
th(RD-PiD)
Note: These become a multiplex bus only when all of the following conditions are satisfied: *BYTE = "H" *Multiplex bus select bit = "1" *While the address which corresponds to chip select signal CS4 is accessed Test conditions (except Port Pi, f(XIN)) * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF * Data input : VIL = 0.8 V, VIH = 2.5 V Test conditions (Port Pi, f(XIN)) * VCC = 5 V10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
107
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
External bus timing when internal memory area is accessed (2- access) in high-speed running
(VCC = 5 V10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) 40 MHz when the clock source select bit = "0") f (XIN) = 40 MHz Symbol Parameter Min. Max. tw(H), tw(L) td(1-WR) td(1-RD) tw(WR) tw(RD) td(A-WR) td(A-RD) td(A-ALE) td(BHE-WR) td(BHE-RD) td(BHE-ALE) td(CS-WR) td(CS-RD) td(CS-ALE) td(WR-DLQ/DHQ)
__ __
Bus timing data formula 1 x 109 f(XIN) - 20
Unit ns ns ns
high-level pulse width, low-level pulse width
___
5 -7 -7 5 5 25 25 10 25 25 10 25 25 10 35 30 4 4 10 10 10 10 10 10 10 15 0 12 12
WR output delay time
___
RD output delay time
___
WR low-level pulse width
___
RD low-level pulse width Address output delay time Address output delay time Address output delay time
____
BHE output delay time
____
BHE output delay time
____
BHE output delay time Chip select output delay time Chip select output delay time Chip select output delay time Data output delay time
1x f(XIN) 1 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 2 x 109 f(XIN) 109
- 20 - 20 - 25 - 25 - 40 - 25 - 25 - 40 - 25 - 25 - 40
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-------- 1x f(XIN) + 5 109 -------- -------- 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) 1 x 109 f(XIN) - 15 - 15 - 15 - 15 - 15 - 15 - 15 - 10
tpxz(WR-DLZ/DHZ) Floating start delay time td(ALE-WR) td(ALE-RD) tw(ALE) th(WR-A) th(RD-A) td(WR-BHE) td(RD-BHE) td(WR-CS) td(RD-CS) th(WR-DLQ/DHQ) ALE output delay time ALE output delay time ALE pulse width Address hold time Address hold time
____
BHE hold time
____
BHE hold time Chip select hold time Chip select hold time Data hold time
tpzx(WR-DLZ/DHZ) Floating release delay time
--------
: f(XIN) 20 MHz when the clock source select bit = "1". : f(XIN) = 20 MHz when the clock source select bit = "1".
108
PR
. . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric otic par N e Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(External bus timing on internal RAM access (2- access) in high-speed running)
tw(H) tw(L) f(XIN) tw(L) 1 tw(H)
tr
tf
tc
tw(H) tw(L)
tr
tf
tc
tw(L) td(1-WR) td(1-WR) tw(H) td(1-RD) td(1-RD)
RD tw(RD)
WR tw(WR) tw(ALE) td(ALE-WR) ALE output tw(ALE) td(ALE-RD)
td(BHE-WR) BHE output td(BHE-ALE) td(A-WR) A0--A7 output A8--A15 output A16--A23 output td(A-ALE) td(CS-WR) CS0--CS4 output td(CS-ALE) Address
th(WR-BHE)
td(BHE-RD)
th(RD-BHE)
th(WR-A)
td(BHE-ALE) td(A-RD) Address td(A-ALE)
th(RD-A)
th(WR-CS)
td(CS-RD) td(CS-ALE)
th(RD-CS)
td(WR-DLQ/DHQ) D0--D7 output D8--D15 output (BYTE = "L") Hi-Z tpzx(WR-DLZ/DHZ) Data
th(WR-DLQ/DHQ) Hi-Z
tpxz(WR-DLZ/DHZ) V The value of output data is undefined. Test conditions * VCC = 5 V10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 100 pF
109
GZZ-SH00-85B<85A0> Mask ROM number
7700 FAMILY MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP 16-BIT MICROCOMPUTER M37754M8C-XXXGP M37754M8C-XXXHP MITSUBISHI ELECTRIC
Date: Receipt Section head Supervisor signature signature
Note : Please fill in all items marked Issuance signatures Company name Date issued 1. Confirmation Specify the name of the product being ordered. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : 27512 0000 0010 1000 DATA DATA 27101 00000 00010 11000 (1) Set "FF16" in the shaded area. (2) Address 016 to 1016 are the area for storing the data on model designation and options.This area must be written with the data shown below. Details for option data are given next in the section describing the STP instruction option. Address and data are written in hexadecimal notation. 60K 4D 33 37 37 35 34 4D 38 Address 0 1 2 3 4 5 6 7 Address Address Option data 10 8 9 A B C D E F (hexadecimal notation) Date: TEL ( Responsible officer Supervisor
Customer
)
60K
FFFF
1FFFF
43 2D FF FF FF FF FF FF
2. STP instruction option One of the following sets of data should be written to the option data address (1016) of the EPROM you have ordered. Check @ in the appropriate box. Address 1016 3. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 100P6S Mark Specification Form (for M37754M8C-XXXGP), 100P6Q Mark Specification Form (for M37754M8C-XXXHP) and attach to the Mask ROM Order Confirmation Form. 4. Comments STP instruction enable STP instruction disable 0116 0016 Address 1016
100P6S (100-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
80 81 51 50
Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
100 1 30
31
B. Customer's Parts Number + Mitsubishi catalog name
80 81 51 50
100 1 30
31
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 14 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, , (periods), (commas) are usable.
.
,
C. Special Mark Required
80 81 51 50
100 1 30
31
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
100P6Q (100-PIN LQFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
75
51 50
76
Mitsubishi IC catalog name Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
100 1 25
26
B. Customer's Parts Number + Mitsubishi catalog name
75
51 50
76
Mitsubishi lot number (6-digit or 7-digit)
100 1 25 26
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 12 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, , (periods), (commas) are usable.
.
,
C. Special Mark Required
75 51 50
76
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
100 1 25
26
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Apr. 1999. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
M37754M8C-XXXGP/HP DATA SHEET
Revision Description Rev. date 971114 980602
1.01 (1) Page 14 is updated. (The previous version of this page cannot be read in.) (2 ) The following are added: *MASK ROM ORDER CONFIRMATION FORM *MARK SPECIFICATION FORM (1) For the "valid output polarity select bit for interrupt request (bit 1 at address 1C16)" (threephase mode 1), it's name and function are corrected: * New bit name in three-phase mode 1: interrupt validity output select bit * Corrected function: 0: Timer B2 interrupt request generated at each even-numbered underflow of timer B2 1: Timer B2 interrupt request generated at each odd-numbered underflow of timer B2 * Related pages: pages 37, 38, 40 (2) For the following register, it's internal status after reset is corrected: * Target register: processor mode register 0 (address 5E16) * Correction: the status of bit 1 is "0". (Not "1".) * Related page: page 63 (3) The names of registers at addresses 5C16, 5D16 are corrected: * Address 5C16: timer B1 mode register * Address 5D16: timer B2 mode register * Related page: page 63 (4) For the "timer A write flag (address 4516)", it's name and it's bit name are corrected: * New register name: timer A write register * New bit name: timer Ai write bit (i = 0 to 2) * Related pages: pages 8, 37, 40, 63
2.00
990428
(1/1)

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